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The Lead Application Engineer will focus on developing solutions in technology, mentoring teams, and driving innovative projects to address complex problems.

Responsible for layout design and validation of analog circuits while analyzing process flows and design rules provided by the foundry, ensuring communication with design engineers to meet layout requirements.

The role involves applying machine learning to optimize verification methodologies, specifically for ASIC pre-silicon verification, collaborating with teams, and engaging with customers on innovative strategies.

Embed with strategic semiconductor customers to deploy LLM- and agent-based AI into end-to-end EDA flows (RTL through signoff). Architect agentic workflows, integrate Cadence AI products, define KPIs for productivity and ROI, guide secure LLM access and infrastructure, run design reviews, and produce reusable playbooks to scale deployments across sites.

Design and develop analog/mixed-signal IC blocks for high-speed SerDes from concept through verification. Responsibilities include circuit design (drivers, receivers, serializers/deserializers, PLLs, ADC/DACs, biasing, regulators), simulation and layout using CAD tools, lab testing, and collaboration with cross-functional teams.

Lead technical design of high-speed SERDES PMA circuits (up to/above 112 Gbps) from concept through verification. Collaborate with physical design and global teams, provide circuit and architecture leadership, and support silicon evaluation.

Lead customer engagements to define AI-assisted verification use cases; design and optimize SystemVerilog/UVM verification environments; develop AI workflows, prompts, and automation; run benchmarks, demos, training, and troubleshooting; collaborate with R&D and product teams and produce technical collateral and best practices.

Prepare quarter-end reporting and audit committee deliverables, validate finance data from SAP/Incorta/CPM/NGA, generate reports and ad hoc analyses, perform data quality reviews and reclasses, support UAT and system enhancements, assist acquisition integrations, and partner with quote-to-cash and cross-functional teams to resolve reporting discrepancies.

The Design Engineering Architect leads complex IP developments, collaborating with system architects, managing RTL design, and improving processes while representing Cadence in standards and conferences.

Lead design and implementation of the SystemVerilog compiler and code generator for Xcelium, optimize front-end and codegen for multi-billion gate designs, perform performance engineering in C++, and prototype innovations like LLM-enhanced, parallel, and distributed compilation.