Responsibilities:
• Engage with customers to understand verification challenges and identify suitable AI-assisted verification use cases. - UVM testbench and component generation - Test and sequence generation - VIP integration and configuration - Assertion and functional coverage generation - Simulation failure triage and root-cause analysis - Log and waveform analysis - Verification flow automation
• Develop and optimize SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC designs.
• Develop reusable prompts, skills, agents, scripts, and AI-assisted workflows for customer applications.
• Conduct technical evaluations, benchmarks, demonstrations, workshops, and customer training.
• Troubleshoot UVM, simulation, AI integration, and verification flow issues.
• Collaborate with R&D, Product Engineering, and support teams to address customer requirements and technical issues.
• Develop technical collateral, AI use cases, reference flows, and best practices.
Qualifications:
• MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Five or more years of experience in digital design, functional verification, or EDA application engineering.
• Strong hands-on experience with SystemVerilog and UVM.
• Experience developing UVM environments, including agents, sequences, scoreboards, reference models, functional coverage, and register models.
• Strong understanding of constrained-random and coverage-driven verification methodologies.
• Experience integrating and debugging Verification IP in UVM-based environments.
• Experience with simulation, debug, coverage analysis, or low-power verification.
• Experience with Cadence tools such as Xcelium, Verisium, or VIP is a strong advantage.
• Strong scripting skills in Python, TCL, shell scripting, or Perl.
• Ability to translate verification challenges into practical and measurable AI-assisted solutions.
• Strong problem-solving, communication, presentation, and customer engagement skills.
Preferred Qualifications:
• Experience architecting reusable UVM environments for complex SoC or subsystem verification.
• Experience applying AI or automation to testbench generation, sequence generation, coverage, debug, or regression analysis.
• Familiarity with LLM APIs, prompt engineering, RAG, vector databases, agent-based workflows, MCP, or tool-calling frameworks.
• Experience deploying AI solutions in cloud-based or on-premises environments.
• Knowledge of CPU, interconnect, memory subsystem, low-power, or UPF verification.
• Familiarity with one or more protocols, including: - AMBA CHI, AXI, or AHB - USB or USB4 - LPDDR or HBM - UFS, UniPro, or M-PHY - PCI Express - DisplayPort or eMMC
We’re doing work that matters. Help us solve what others can’t.Skills Required
- MS degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Five or more years of experience in digital design, functional verification, or EDA application engineering.
- Strong hands-on experience with SystemVerilog and UVM.
- Experience developing UVM environments including agents, sequences, scoreboards, reference models, functional coverage, and register models.
- Strong understanding of constrained-random and coverage-driven verification methodologies.
- Experience integrating and debugging Verification IP in UVM-based environments.
- Experience with simulation, debug, coverage analysis, or low-power verification.
- Strong scripting skills in Python, TCL, shell scripting, or Perl.
- Ability to translate verification challenges into practical and measurable AI-assisted solutions.
- Strong problem-solving, communication, presentation, and customer engagement skills.
- Experience with Cadence tools such as Xcelium, Verisium, or VIP.
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
