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Develop and maintain advanced verification environments using SystemVerilog/UVM/OVM; design UVM agents and behavioral models; implement assertions and coverage; create random and directed tests; debug simulation failures and analyze coverage; collaborate with design teams on SoC/IP verification.

Lead chip-level digital architecture, own top-level RTL and integration, drive timing/CDC constraints and front-end flows, coordinate cross-discipline teams through tape-out, and mentor engineers while supporting post-silicon bring-up and validation.

Customer-facing architect for VMware Cloud Foundation and vKS who designs and validates SDDC deployments, integrates physical underlay (Cisco ACI) with NSX overlays, architects Kubernetes networking and enterprise load balancing (AVI, F5, Netscaler), leads discovery workshops and POCs, and produces reusable reference architectures to accelerate private cloud adoption.

The ASIC Design Engineer is responsible for leading complex design implementations, ensuring quality through peer reviews, and adapting to technology changes.

The ASIC Design Engineer leads design implementations, ensuring quality in multiple disciplines including synthesis, floorplanning, and timing closure with minimal supervision.

The Supply Chain Planning Analyst will support planning efforts, manage ERP issues, forecast production, and drive improvements in manufacturing processes at Broadcom.

Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.

Lead and execute backend digital physical design for SoC (5nm and below): floorplanning, placement, CTS, routing, extraction, physical verification, STA closure, timing/functional ECO, and automation of P&R flows using industry EDA tools.

Lead and execute backend digital physical design for SoC at 5nm and below: floorplanning, placement, CTS, routing, extraction, STA closure, ECOs, physical verification, and automation of EDA flows.

Lead and execute backend digital physical design for SoC at 5nm and below: floorplanning, placement, CTS, routing, extraction, physical verification, STA closure, timing/functional ECO, and automation of EDA flows using Cadence/Synopsys/Mentor toolchains.