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Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.

The Epitaxy Fab Assistant performs functions related to Epi wafers, operating reactors and supporting tools, and calibrating process equipment in a fab environment.

Develops and deploys semiconductor timing sign-off flows using Python, Perl, Tcl, and Unix shell. Responsibilities include EDA flow development for PrimeTime, Tempus, Innovus, and RedHawk; automation; statistical data analysis and modeling; and support for chip design teams. The role requires advanced digital IC design expertise, strong communication, multitasking, problem-solving, and collaboration across projects.

Develop and deploy advanced timing sign-off methodologies for SOC, 3D/2.5D IC, and multi-die designs. Lead EDA flow development using Primetime, Tempus, and Innovus, while applying statistical analysis, silicon technology, testability, and yield expertise. The role requires extensive tapeout and timing sign-off experience, scripting and automation skills, cross-functional collaboration, and autonomous problem solving in a fast-paced engineering environment.

Design and verify mixed-signal circuits, IO interfaces, analog blocks, and digital wrappers in advanced CMOS technologies. Collaborate with layout and test engineers on physical design, characterization, silicon validation, and test-chip infrastructure. Interface with customers to define requirements and specifications, support ATE and bench testing, and produce datasheets, application notes, and integration guides.

Design and develop memory and circuit blocks at gate or transistor level for AI foundation IP. Responsibilities include circuit simulation, layout extraction, post-layout verification, physical implementation, characterization flow integration, automation scripting, memory model verification, documentation, and silicon test correlation. The role requires expertise in transistor-level behavior, device physics, signal integrity, EM/IR, reliability analysis, simulation tools, and memory circuit design, with DFT and chip integration knowledge preferred.

Designs and analyzes memory architectures and transistor-level circuit blocks, including layout, physical implementation, post-layout verification, characterization, and behavioral and physical memory models. Develops automation scripts for simulation and verification, documents specifications and timing, supports DFT and chip integration, and creates silicon test plans. The engineer also correlates silicon results with simulations and assists with silicon debug.

Lead product definition, design, test, and characterization for isolation products. Drive R&D programs with cross-functional teams, perform yield analysis and failure investigations, establish test setups and ATE testing, and support validation and manufacturing handoff to achieve quality, yield, and reliability targets.

Lead facet coating process integration for optoelectronic lasers and detectors. Develop and scale multilayer IBS/ALD coatings, run DOE/SPC/FMEA, perform metrology (ellipsometry, AFM, spectrophotometry), drive CAPA/root-cause analyses, manage equipment lifecycle and subcontractor performance, implement KPIs/dashboards, and collaborate with Product, Quality, and R&D to improve yield, reliability, and production efficiency in a 24/7 manufacturing environment.

Lead a team of IC design engineers to develop motion control sensor ASICs end-to-end. Own technical architecture, design, tape-out, customer trials, field issue resolution, and product sustainability. Manage people and projects, and collaborate cross-functionally with optics, magnetic, mechanical, electrical, and manufacturing engineers in a fast-paced environment.