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Leads custom analog layout and verification for high-speed SerDes and memory I/O circuits in advanced semiconductor nodes. Collaborates with design teams on circuit implementation, supports IP and chip-level integration, assists with customer requirements and IP delivery, and applies high-speed layout techniques involving matching, parasitic minimization, power grids, ESD, EM, and IR-drop analysis.

Plan production against customer demand, capacity, inventory, and delivery targets. Maintain master schedules, prepare manufacturing purchase orders, coordinate supply chain partners, track operational metrics, manage WIP reconciliation, support forecasting and Sales and Operations Planning, and identify delivery risks. The role also supports new production introduction, invoice reconciliation, customer order commitments, and recovery planning in a high-volume semiconductor or electronics manufacturing environment.

Develop, test, maintain, and debug embedded firmware for silicon products. Build robust software test suites, migrate and consolidate silicon debug software, support silicon design infrastructure, and optimize low-level code for real-time performance. The role requires embedded C/C++ development, RTOS experience, hardware and peripheral interfacing, cross-platform development, software validation, modern CI workflows, and collaboration across firmware and hardware teams.

Own PCB layout for complex high-speed board products from floorplanning through fabrication and assembly release. Translate schematics into DFM-compliant layouts, define stackups and impedance requirements, apply SI/PI, thermal, mechanical, EMC/EMI, and PDN principles, and generate verified Gerber, ODB++, drill, assembly, and BOM outputs. Collaborate with hardware, SI/PI, fabrication, and assembly partners while managing layout milestones and quality processes.

Research and develop analog and signal-processing techniques for simultaneous bidirectional communication over high-speed copper serial links. Build behavioral channel and transceiver models, study self-interference cancellation, evaluate channel impairments and non-idealities, and design and simulate circuit building blocks using Python or circuit-level CAD tools. The intern will assess data rates, energy efficiency, and implementation complexity, then present findings in a technical report and oral presentation.

Define firmware architecture for high-speed 224G/lane AEC retimers, including boot, calibration, link training, equalization, FEC, telemetry, and standards compliance. Lead silicon bring-up from first samples through production while partnering with ASIC and signal-integrity teams. Implement IEEE 802.3ck/dj adaptation algorithms, PAM4 equalization, FEC integration, and predictive telemetry on constrained MCUs. The role requires embedded C, assembly, Python tooling, RTOS experience, hardware-in-loop testing, and up to 15% travel.

Develop, test, and maintain real-time embedded firmware for Kandou AI ASIC products. Responsibilities include firmware design on heterogeneous SoCs, board and SoC bring-up, bootloaders, secure boot, hardware interfacing, debugging, firmware updates, and support for silicon design workflows. The role collaborates with architects and lead engineers while promoting modern testing, automation, integration, code review, and delivery practices.

Own the SoC and product specification stack for a 1.6T retimer SoC and AEC products operating at 224G/lane PAM4. Author normative, traceable specifications for RTL, firmware, software, SI/PI, manufacturing, qualification, and customer engineering teams. Represent architecture in hyperscaler and strategic customer negotiations, covering qualification testing, FEC telemetry, CMIS vendor pages, and thermal commitments.

The DFT Engineer will implement hierarchical MBIST, scan, boundary scan, and IJTAG methodologies; generate ATPG patterns; analyze fault coverage; perform timing simulations; define test-mode constraints; debug silicon issues; and collaborate with test and production engineering teams during device probe and final-test bring-up. The role requires strong debugging, scripting, communication, and semiconductor design-for-test experience.

Develop and maintain digital design verification environments for complex FPGA and ASIC designs. Create verification plans, test benches, regression frameworks, and coverage strategies; perform simulation, debugging, and design validation; collaborate with designers, participate in reviews, track defects, and close verification issues. The role also involves project planning, constrained-random testing, UVM, and potentially SerDes and high-speed protocol verification.