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The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Customer-facing firmware applications engineer for Leo CXL Smart Memory Controllers. Provide firmware bring-up, validation, debugging, and performance tuning (DDR/PCIe/CXL). Develop Python test automation, collaborate with cross-functional teams, produce customer-facing documentation, and support customers from early silicon through production ramp. Onsite in San Jose, CA.

Astera Labs seeks talented professionals in various disciplines for future openings, focusing on hardware, firmware, software, program management, and operations.

The Principal Product Applications Engineer will engage with customers, support PCIe product adoption, troubleshoot system issues, and create technical documentation while collaborating with cross-functional teams.

The Principal Physical Design Engineer will oversee end-to-end STA ownership, coordinating and executing design processes for connectivity ASICs while ensuring robust timing closure and collaboration with various engineering teams.

Drive customer success for Taurus Ethernet solutions through technical engagement, debugging complex issues, and collaborating with internal teams for product evolution.

Lead RTL design and implementation for connectivity silicon blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design teams to achieve timing closure, CDC, lint, and low-power goals. Mentor engineers, debug pre- and post-silicon issues, and drive methodology for timely tapeouts.

Lead advanced packaging R&D for photonics products, defining process flows (wafer/panel/die), integrating EIC-to-PIC, qualifying materials and equipment, partnering with OSATs and vendors, and driving yield, reliability, PDKs, and packaging design rules for NPO/CPO products.