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Lead development of high-speed electrical connectivity products and manage cross-functional engineering teams while overseeing the product lifecycle from concept to launch.

Lead hardware design engineering for active electrical cables and smart cable modules, overseeing teams in design, validation, and customer integration. Develop technological strategies and manage product lifecycles from concept to production while fostering engineering excellence and collaboration.

The Senior Firmware Engineer will architect and develop firmware for SoC and systems, working with hardware and ensuring customer needs are understood and met.

Lead the go-to-market strategy for fabric switch and memory controller solutions, focusing on product positioning and market intelligence while collaborating with cross-functional teams and mentoring a marketing team.

The Product Quality Engineer will perform failure analysis, drive root-cause identification, collaborate with teams, and utilize lab instrumentation to ensure high-quality AI connectivity solutions.

As a Senior Digital Design Engineer, you will design and implement CPU subsystems and collaborate with teams on verification, quality, and automation improvements in high-performance AI connectivity solutions.

Lead SI/PI planning, design, simulation, and lab validation for high-speed connectivity products. Perform EM and PI simulations, hardware constraint definition, debug root-cause issues, and collaborate cross-functionally to deliver PCIe/Ethernet/SERDES channel solutions.

Debug and integrate firmware for Ethernet retimers/gearboxes, triage lab and field failures, fix embedded C/C++ firmware, support customer bring-up, and develop features for SERDES, link training, equalization, and diagnostics.

Lead architecture and execution of UVM/SystemVerilog verification for multi-Gbps SerDes/PHY IP. Define verification strategy, implement testbenches and RNM co-simulation, drive coverage closure, debug with designers, and mentor junior engineers to ensure first-pass silicon success across PCIe/UALink/UCIe/Ethernet/CXL protocols.

Lead formal verification strategy and methodology for next-generation connectivity products. Develop formal models, assertions, and test plans; apply EDA tools and complexity-reduction techniques to find corner-case bugs. Mentor global engineers, collaborate with design teams, and represent the company in industry forums.