Top Tech Jobs & Startup Jobs

Lead end-to-end development of internal automation platforms, including backend services, databases, frontend features, access controls, approval workflows, integrations, dashboards, and systems of record. Partner with IT, HR, and Finance to automate onboarding, offboarding, asset tracking, entitlement management, and audit processes. Own architecture, schema evolution, testing, engineering standards, and technical direction while personally delivering production code using AI-assisted development tools.

Lead the architecture and optimization of cloud-native HPC, CI/CD, and automation infrastructure for semiconductor design workflows. Manage cloud compute, scheduling, EDA integrations, data lakes, telemetry, dashboards, and AI-assisted failure analysis while reducing cost and improving reliability. Drive automation across engineering, HR, Legal, and Finance processes, including employee lifecycle, approvals, access provisioning, spend tracking, and compliance controls. Establish enterprise automation strategy and advise senior stakeholders on infrastructure investment and roadmap.

Executes signal and power integrity planning, design, electromagnetic modeling, simulation, and laboratory validation for high-speed connectivity products. The role covers PCIe and Ethernet PCB/interconnect challenges, SERDES channel simulation and equalization, BGA and connector modeling, power integrity analysis, measurement with advanced test equipment, and debugging. The engineer defines system constraints and technology roadmaps, collaborates cross-functionally, leads root-cause investigations, and works onsite in a hands-on principal-level capacity.

Own physical design and signoff for complex connectivity ASICs from RTL through GDS. Drive synthesis, place-and-route, extraction, timing closure, ECOs, EM-IR, Formality, and DRC/LVS across blocks and full chips. Collaborate with RTL, verification, implementation, and top-level teams on constraints, clocking, I/O timing budgets, hierarchical models, and convergence. The role requires advanced-node experience, high-speed SERDES/DDR knowledge, scripting, and proficiency with Cadence or Synopsys toolchains.

Own functional verification of high-speed SerDes and PHY IP for AI connectivity platforms. Architect UVM environments, define coverage and sign-off strategies, develop SystemVerilog testbenches, verify equalization, CDR, training, and link bring-up, and drive coverage closure through tape-out. Collaborate with analog, digital, SoC, firmware, post-silicon, and customer teams on AMS co-simulation, RNM, emulation, and protocol compliance. Mentor junior engineers and lead verification methodology and IP reuse improvements.

Develop and support complex mixed-signal SoC ATE test solutions from design and initial samples through high-volume production. Define test strategies and plans, select tester platforms, develop wafer-sort and final-test hardware and programs, optimize test coverage and time, and lead silicon bring-up, debug, and bench-to-ATE correlation. Collaborate with design and manufacturing partners while testing high-speed SerDes and connectivity protocols.

Leads and grows the ATE Test Engineering organization, defining test strategies for high-speed mixed-signal and SoC products from silicon bring-up through high-volume manufacturing. Oversees wafer-sort and final-test hardware, ATE program development, characterization, debug, coverage, yield, cost, and test-time optimization. Partners with design, DFT, product engineering, operations, and manufacturing teams to deliver production-ready connectivity products and improve quality and execution.

Leads complex analog/mixed-signal semiconductor programs from specification through tape-out and silicon validation. Responsibilities include developing schedules, managing milestones, budgets, dependencies, risks, and deliverables; coordinating circuit design, layout, verification, validation, systems, operations, foundries, and vendors; leading program reviews; communicating status and trade-offs; and improving program management processes.

Leads mechanical architecture and system integration for rack-scale AI infrastructure, GPU platforms, networking systems, optical connectivity, and air- or liquid-cooled systems. Defines rack layouts, mechanical interfaces, packaging, cable management, cooling integration, manufacturability, serviceability, and design requirements. Collaborates with electrical, thermal, power, silicon, software, manufacturing, product, and ODM teams to drive system integration, validation, cost optimization, and production readiness.

Own immigration case management end-to-end, manage external immigration service providers, and lead cross-functional HR operations projects. Build and document SOPs, dashboards, and automated workflows using Microsoft tools. Partner with HR, Legal, Talent Acquisition, IT, and Finance to ensure compliant, scalable processes and strong stakeholder communication.