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Lead the SIPI engineering team to develop high-performance IC packaging solutions, partner across teams, and drive execution from concept through production.

Design and optimize power delivery systems for ASIC products, ensuring robust integrity and developing board-level designs while collaborating with vendors and teams.

Lead the development of high-speed semiconductor products, focusing on post-silicon product development, RF testing, and characterizing advanced semiconductor solutions.

The Firmware Engineering Manager will oversee BootROM firmware development and simulation modeling, ensuring robust integration of security features and hardware/firmware co-design.

Lead SI/PI planning, design, simulation, and lab validation for high-speed connectivity products. Perform EM and PI simulations, hardware constraint definition, debug root-cause issues, and collaborate cross-functionally to deliver PCIe/Ethernet/SERDES channel solutions.

Coordinate cross-functional teams and contract manufacturers to plan and manage cable and paddle-card NPI. Maintain SKU-level demand, supply, and build plans; manage FG/WIP, logistics and material movement; identify and resolve manufacturing and logistics roadblocks to meet delivery schedules.

As a Principal Embedded Software Engineer, you will develop and maintain firmware for Ethernet retimers and gearboxes, and support customer integration efforts, emphasizing high-speed connectivity in AI infrastructure.

The Principal Engineering Program Manager leads ASIC product development from concept to production, ensuring on-time, on-spec, and on-budget delivery while managing cross-functional teams and stakeholder alignment.

Design, implement, and test production-grade diagnostics and manufacturing tests for high-speed datacenter boards and ASICs. Bring up newly manufactured boards, perform root-cause analysis, support platform software/hardware features, and coordinate with hardware engineering through design, validation, and mass-production stages.

Lead RTL-to-GDS physical implementation and signoff for complex connectivity SoCs. Drive PnR, timing closure, extraction, EM-IR, DRC/LVS, and ECO flows; collaborate with RTL, verification, and IP teams to resolve issues and achieve full-chip signoff.