Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
About the Role
As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners — owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp.
Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams.
This position is required onsite in San Jose, CA.
Key Responsibilities
- Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms
- Develop, validate, and debug firmware using C and Python across Leo's PCIe/CXL and DDR memory subsystems
- Spearhead internal and external discussions on design requirements of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS (Reliability, Availability, Serviceability) features, and performance tuning
- Serve as the primary firmware technical point of contact for key customer accounts (hyperscalers, OEMs), driving issue resolution and feature demonstrations
- Interpret and implement requirements from CXL, PCIe, and JEDEC DDR specifications into robust firmware solutions
- Collaborate with cross-functional teams (FW engineering, HW, systems, product management) to deliver firmware releases and customer collateral on schedule
- Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools to support validation and customer debug workflows
- Contribute to technical documentation including application notes, release notes, design guides, and customer-facing collateral
- Represent the Leo team in customer technical reviews, design-in engagements, and industry forums
Basic Qualifications
- Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field; Master's degree preferred
- 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC/silicon products for Server, Storage, and/or Networking applications
- Professional attitude with the ability to prioritize a dynamic list of tasks and work with minimal guidance
- Entrepreneurial, open-minded behavior and can-do attitude — think and act fast with the customer in mind!
- Authorized to work in the US and available to start immediately
Required Experience
- High proficiency in C for embedded firmware development in RTOS environments
- Working knowledge of CXL (Compute Express Link) — CXL 1.1/2.0/3.0 — including memory expansion, pooling, and sharing concepts
- Proficiency in Python for scripting, test automation, and diagnostic tooling
- Deep hands-on knowledge of high-speed memory interfaces — DDR4 and/or DDR5 DRAM — including initialization sequences, training algorithms, timing margins, and ECC/RAS features
- Experience with firmware bring-up, debug, and validation of memory or I/O subsystems on server platforms
- Strong debugging skills with the ability to triage and root-cause issues in complex embedded systems
- Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems
- Experience working with developer workflows: SCM (preferably Git), code reviews, CI/CD pipelines
Preferred Experience
- Experience with PCIe endpoint firmware at the PHY, Link, and Transaction layers; familiarity with PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling
- Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other lab debug equipment
- Familiarity with BIOS/BMC/OS interactions with PCIe/CXL devices and MMIO/RAS concepts
- Experience with server memory performance tuning — latency and bandwidth optimization
- Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus
Compensation
The base salary range for this role is $175,000 – $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Astera Labs is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field
- 8+ years of experience in firmware development or product applications engineering
- High proficiency in C for embedded firmware development
- Working knowledge of CXL 1.1/2.0/3.0
- Proficiency in Python for scripting and automation
- Deep knowledge of high-speed memory interfaces DDR4/DDR5
- Debugging skills in complex embedded systems
- Familiarity with SoC interfaces and developer workflows
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
