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The Senior Principal Digital Design Engineer leads digital design architecture for AI connectivity, guiding teams through design execution and cross-functional collaboration while mentoring engineers to ensure high-quality production deliveries.

Lead architecture and development of firmware and microcontroller subsystems for SoC and system products. Implement differentiating features, collaborate with logic designers to define and verify HW–SW interfaces, develop on-chip MCU firmware and C-based SDKs for system controllers (BMC), debug PCIe protocol issues, automate workflows with Python, and maintain build/documentation toolchains. Customer-facing and requires strong prioritization.

Seeking a Senior Principal Product Manager to lead product roadmap for Astera's connectivity solutions, involving software, firmware, and silicon integration. The role includes engaging with customers, defining strategies, and overseeing cross-functional execution to improve manageability in AI infrastructure.

Lead full-cycle recruiting for hardware, silicon, and semiconductor engineering roles. Source and close passive candidates, partner with engineering leaders on hiring strategy, build proactive talent pipelines, drive process improvements and documentation, and champion inclusive hiring to scale critical technical teams in a hyper-growth environment.

The Principal Product Application Engineer will lead firmware development and customer engagement for CXL Smart Memory Controllers, ensuring seamless integration and resolution of firmware issues while collaborating with various engineering teams.

The Principal Emulation Engineer will verify protocols on ASICs, create testing environments, and debug hardware-software interfaces, focusing on communication protocols like PCIe and Ethernet.

Lead and develop next-generation high-speed semiconductor products, focusing on product and test engineering, circuit design, and problem-solving.

Lead and execute RTL-to-GDS physical implementation for advanced-node connectivity SoCs: floorplan, placement, CTS, routing, timing/power signoff, verification, ECO/tapeout, and mentor engineers while partnering cross-functionally to define methodology and ensure production-quality deliverables.

Customer-facing firmware applications engineer for Leo CXL Smart Memory Controllers. Provide firmware bring-up, validation, debugging, and performance tuning (DDR/PCIe/CXL). Develop Python test automation, collaborate with cross-functional teams, produce customer-facing documentation, and support customers from early silicon through production ramp. Onsite in San Jose, CA.

Astera Labs seeks talented professionals in various disciplines for future openings, focusing on hardware, firmware, software, program management, and operations.