Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle.
As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers.
Location - San Jose, CA OR Israel
Key Responsibilities
- Product Technical Ownership
- Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement
- Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met
- Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures
- Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths
- Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.
- Cross-Functional Technical Leadership
- Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest
- Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria
- Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies
- Work closely with physical design teams on timing closure, power optimization, and backend execution
- Process Excellence & Organizational Development
- Establish and reinforce scalable processes, documentation, and handoffs that support company growth
- Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line
- Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration
- Model steady, calm leadership, particularly in high-stakes or ambiguous situations
- Shape engineering culture and talent strategy to support Astera's rapid growth trajectory
Basic Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience across architecture, silicon design, validation, systems, or related domains
- Proven track record of developing large-scale chips (300mm²+) through successful tapeout
- Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures
- Strong understanding of RTL design, design verification, DFT, and physical design flows
- Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures
- Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership
- Strong communication and executive presence with the ability to influence at all levels of the organization
Preferred Qualifications
- Master's degree in Electrical Engineering or Computer Engineering
- Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures
- Experience with advanced process nodes (7nm, 5nm, or below)
- Background in power management, clocking architectures, or high-speed analog integration
- Experience operating in fast-growing startups or hyper-scale environments
Key Leadership Competencies
- Systems Thinking: See the big picture while managing details
- Emotional Intelligence: Calm under pressure, empathetic, and influential
- Adaptability: Thrive in ambiguity and fast-changing environments
- Execution Discipline: Deliver predictable results without sacrificing innovation
Base salary range is $260,000 to $295,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience across architecture, silicon design, validation, systems, or related domains
- Proven track record of developing large-scale chips (300mm²+) through successful tapeout
- Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures
- Strong understanding of RTL design, design verification, DFT, and physical design flows
- Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures
- Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership
- Strong communication and executive presence with the ability to influence at all levels of the organization
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
