Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes.
Astera Labs is seeking a Principal Product Applications Asia Region Lead with 8+ years of experience supporting the development and design-in of semiconductor products for PCIe/CXL. Regional leads focus on development, debugging, and design-in activities related to customers in a designed geography, and help coordinate with local development teams in Astera Labs Headquarters. This role will be supporting our China region. Role is required to work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone.
Basic Qualifications
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.
- Minimum of 3 years’ experience in designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
- Full professional proficiency in Mandarin (written and spoken) required to communicate directly with Asia region customer contacts
Required Experience
- Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 5.0 at a minimum, some experience with 6.0/CXL preferred.
- Silicon/System bring-up and debug experience in customer systems.
- Technical ownership of issue resolution: Driving and directing internal teams toward issue resolution. Driving communication with customers, FAEs, and sales team members
- Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.
- Comfort working with software/firmware associated with semiconductor products, such as: Firmware development with C-language, scripting with Python or other equivalent programming languages.
Preferred experience
- Triaging complex customer reported issues which require taking into account multiple layers of conditions. For instance, silicon, firmware, hardware board design, and system environment.
- Experience with common data center BMC implementation, and BIOS configuration
- Development/support for PCIe or Ethernet Switch or Retimer products.
- PCIe compliance testing methodology and troubleshooting.
- Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.
- Mandarin language proficiency preferred. Candidate must be able to speak Mandarin to effectively communicate with our China region customers and team members.
- Candidate will need to be open work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone
Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering
- At least 3 years of experience designing in complex SoC or silicon products with high-speed interfaces, preferably PCIe
- 8+ years of experience supporting semiconductor product development and design-in
- Professional proficiency in written and spoken Mandarin
- Strong knowledge of PCIe LTSSM, physical-layer standards, and debugging
- Recent PCIe 5.0 experience
- Silicon or system bring-up and debugging experience in customer systems
- Experience driving technical issue resolution across internal teams, customers, FAEs, and sales
- Hands-on experience with protocol analyzers, exercisers, high-speed oscilloscopes, or BERTs
- Experience with C firmware development and Python or equivalent scripting
- Master's degree in Electrical Engineering
- PCIe 6.0 or CXL experience
- Experience triaging issues involving silicon, firmware, hardware, and system environments
- Experience with data center BMC implementation and BIOS configuration
- Experience supporting PCIe or Ethernet switch or retimer products
- PCIe compliance testing and troubleshooting experience
- Understanding of servers, JBODs/JBOGs, networking switches, routers, and interconnects
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
