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Oversee planning and execution of physical design for ASICs, collaborating with designers and engineers in developing cutting-edge connectivity solutions for cloud services.

The Senior Foundry Engineer will focus on silicon process correlation, tapeout readiness, yield improvement, and technical interactions with foundry partners for advanced semiconductor products.

Debug and integrate firmware for Ethernet retimers/gearboxes, triage lab and field failures, fix embedded C/C++ firmware, support customer bring-up, and develop features for SERDES, link training, equalization, and diagnostics.

Lead architecture and execution of UVM/SystemVerilog verification for multi-Gbps SerDes/PHY IP. Define verification strategy, implement testbenches and RNM co-simulation, drive coverage closure, debug with designers, and mentor junior engineers to ensure first-pass silicon success across PCIe/UALink/UCIe/Ethernet/CXL protocols.

Define and measure scale-up fabric performance for GPU clusters by building roofline models, benchmarks, and end-to-end workload studies. Run and scale real inference workloads, identify bottlenecks, perform head-to-head comparisons, and build automated test infrastructure. Partner with cross-functional teams to influence architecture, firmware, and product decisions and produce customer-facing performance reports and documentation.

Lead IR drop and electromigration (EMIR) analysis and sign-off for advanced-node SoCs from floorplan through tapeout. Collaborate with power grid, floorplan, package, implementation, RTL, STA, IP vendors and foundry to resolve hotspots, guide mitigation (decap, grid reinforcement), and deliver automated EMIR flows, runsets, and root-cause reporting for multi-corner sign-off.

Define, develop, and maintain RTL-to-GDSII physical design flows and automation across Cadence and Synopsys toolchains. Integrate foundry runsets, enable multi-corner/multi-mode STA and EMIR infrastructure, optimize PPA and schedules, build QoR frameworks, and support/scale the PD team through standards, tooling, training, and documentation.

Lead sourcing strategy for silicon supply chain nodes (foundry, OSAT, substrates, test). Develop should-cost and TCO models, negotiate complex agreements, manage supplier relationships and SRM, align sourcing with engineering roadmaps, and drive cost savings and risk mitigation.

Provide legal support for commercial transactions including drafting, negotiating, and managing customer, vendor, partnership, and licensing agreements. Partner with sales, procurement, finance and operations to structure deals, build contract playbooks and templates, improve legal processes (including AI tools), train stakeholders, and support strategic initiatives such as M&A diligence and real estate.

Lead end-to-end corporate development transactions (acquisitions, investments, partnerships), perform valuation and strategic analysis, manage diligence and integration across functions, produce board-ready materials, and monitor AI infrastructure market trends to inform executive strategy.