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Lead front-end digital design for high-performance switch ASICs, translating microarchitecture into RTL and owning blocks through synthesis, timing closure, verification, DFT, physical implementation, and GDS delivery. Partner with cross-functional teams on high-speed connectivity protocols, silicon bring-up, lab debugging, and root-cause analysis. Provide technical leadership across complex SoC projects supporting AI infrastructure, networking, server, and storage applications.

Leads functional verification for advanced ASICs and SoCs across planning, test development, simulation, emulation, debugging, coverage analysis, and closure. Develops directed and constrained-random SystemVerilog/UVM tests, collaborates with software, systems, and RTL teams, and drives verification methodologies for server and networking applications. The role also addresses switching architectures, packet processing, PCIe, Ethernet, NoC, and hardware-software co-verification.

Provides technical guidance to ODMs developing semiconductor products, especially PCIe and CXL solutions. Responsibilities include customer-system bring-up and debugging, resolving complex silicon, firmware, hardware, and system issues, directing internal teams, creating technical documentation, supporting compliance testing, and engaging global customers onsite. The role also requires extensive lab work with high-speed test equipment and collaboration with sales, FAE, and engineering teams.

Lead design verification for complex ASIC and SoC connectivity silicon. Develop verification plans, UVM-based SystemVerilog testbenches, assertions, scoreboards, coverage models, and regression automation. Verify PCIe, UALink, and UCIe switching behavior through directed and constrained-random testing. Debug simulation failures, close functional and code coverage, support issue isolation and silicon bring-up, and communicate verification status, risks, and recommendations to technical stakeholders.

Develop and execute verification strategies for connectivity ASICs and SoCs supporting PCIe, UALink, and UCI protocols. Build UVM-based SystemVerilog testbenches, test scenarios, assertions, scoreboards, and coverage models. Debug simulation failures, drive functional and code coverage closure, automate regressions, and collaborate with architecture, RTL, firmware, design, and post-silicon teams on root-cause analysis and silicon readiness.

Develop front-end digital designs for high-performance network controllers, including microarchitecture, RTL, synthesis, IP integration, verification, timing closure, DFT, and GDS ownership. The role requires expertise in PCIe, UALink, ESUN, and Ethernet protocols, Synopsys or Cadence design flows, UVM verification, silicon bring-up, and small-geometry CMOS. Candidates will support complex networking or server/storage SoC products and collaborate with customers and cross-functional teams.

Leads high-priority cross-functional business and technical programs across strategic sales opportunities, product development, semiconductor supply chains, and AI infrastructure initiatives. Establishes accountability, tracks risks and dependencies, drives issue resolution, prepares executive reporting, and develops customer and market intelligence. Partners with senior leadership, Sales, Product, Engineering, FAE, Operations, and Supply Chain teams to accelerate growth and improve execution.

Leads functional verification for high-speed SerDes and PHY IP used in AI connectivity products. Responsibilities include architecting UVM environments, developing SystemVerilog testbenches, driving coverage closure, validating physical-layer protocols and link training, supporting analog/mixed-signal co-simulation and RNM, debugging regressions, and mentoring verification engineers. The role collaborates with analog designers, SoC integration, firmware, post-silicon validation, and customer engineering teams.

Lead front-end digital design for high-performance PCIe, CXL, UALink, and Ethernet devices from requirements and architecture through RTL, verification, tape-out, and shipment. Manage and mentor 6–8 digital design engineers, establish RTL quality standards and signoff processes, resolve performance, power, area, clocking, and integration issues, and coordinate execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

Own the architecture, micro-architecture, RTL implementation, verification, timing closure, DFT, IP integration, and silicon bring-up of complex digital blocks for advanced AI connectivity SoCs. Collaborate with verification, physical design, firmware, and post-silicon teams to deliver production-quality designs using advanced CMOS nodes. Mentor engineers and improve design methodologies and CAD automation.