Principal Verification Engineer

Posted 2 Days Ago
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San Jose, CA, USA
In-Office
185K-230K Annually
Senior level
Big Data • Information Technology
The Role
Leads functional verification for advanced ASICs and SoCs across planning, test development, simulation, emulation, debugging, coverage analysis, and closure. Develops directed and constrained-random SystemVerilog/UVM tests, collaborates with software, systems, and RTL teams, and drives verification methodologies for server and networking applications. The role also addresses switching architectures, packet processing, PCIe, Ethernet, NoC, and hardware-software co-verification.
Summary Generated by Built In

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.


Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.

Key Responsibilities

  • Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
  • Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
  • Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
  • Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
  • Work with RTL designers to troubleshoot and resolve design issues.
  • Drive verification strategy and methodology for SoCs in server and networking applications.

Required Qualifications

  • Bachelor’s degree in Electrical Engineering (Master’s preferred).
  • 8+ years of experience in SoC verification, particularly for server and networking applications.
  • Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
  • Proficiency with industry-standard simulators, version control, and regression systems.
  • Strong debugging and coverage analysis skills.
  • Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
  • Familiarity with verification of switching architectures, including packet processing and forwarding engines.
  • Excellent communication skills and ability to work independently with minimal supervision.

Preferred Qualifications

  • Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
  • Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
  • Knowledge of Ethernet/PCIe switching and central buffer architectures.
  • Experience with emulation platforms and hardware-software co-verification

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Skills Required

  • Bachelor's degree in Electrical Engineering
  • Master's degree in Electrical Engineering
  • 8+ years of experience in SoC verification, particularly for server and networking applications
  • Expertise in SystemVerilog and UVM
  • Hands-on experience across the full verification lifecycle
  • Proficiency with industry-standard simulators, version control, and regression systems
  • Strong debugging and coverage analysis skills
  • Experience developing and executing test sequences, generating stimuli, and identifying verification holes
  • Familiarity with verification of switching architectures, including packet processing and forwarding engines
  • Excellent communication skills and ability to work independently with minimal supervision
  • Experience with third-party Verification IP for PCIe, Ethernet, and InfiniBand
  • Background in Network-on-Chip architectures for smart NICs and AI accelerators
  • Knowledge of Ethernet/PCIe switching and central buffer architectures
  • Experience with emulation platforms and hardware-software co-verification

Astera Labs Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.

  • Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
  • Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
  • Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.

Astera Labs Insights

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The Company
HQ: San Jose, CA
148 Employees
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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