Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.
This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams. You will help advance scalable fabric solutions built around UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet as Astera Labs continues to deliver purpose-built connectivity for demanding AI workloads.
Key ResponsibilitiesDigital Architecture and RTL Design
Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
Develop front-end design solutions for high-performance networking and server connectivity applications.
Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.
Design Implementation and Signoff
Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.
Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.
Verification, Bring-Up, and Technical Leadership
Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.
Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.
Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.
Bachelor’s degree in Electrical Engineering or a related field.
5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.
Experience owning blocks from architecture through GDS and working with Synopsys and/or Cadence design tools and flows.
Authorized to work in the United States.
Master’s degree in Electrical Engineering or a related field.
Experience developing or supporting PCIe or Ethernet switch products.
Familiarity with UVM-based design verification and coverage-driven debug.
Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.
Scripting experience with Python or comparable programming languages, along with a collaborative, customer-focused approach.
Salary range is $175,500 to $195,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering or a related field
- 5-8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications
- Hands-on experience with UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet
- Front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT
- Experience owning blocks from architecture through GDS
- Experience with Synopsys and/or Cadence design tools and flows
- Authorization to work in the United States
- Master's degree in Electrical Engineering or a related field
- Experience developing or supporting PCIe or Ethernet switch products
- Familiarity with UVM-based design verification and coverage-driven debug
- Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below
- Scripting experience with Python or comparable programming languages
- Collaborative, customer-focused approach
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
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