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Designs, verifies, integrates, tests, and supports memory controller silicon IP. Responsibilities include preparing IP deliveries, integrating third-party IP, debugging simulation failures, developing new RTL functionality, and providing customer support.

Architects high-performance PCIe controller silicon IP for data center and AI applications. Owns architecture specifications, drives technical reviews, collaborates with design, verification, physical design, product, marketing, field, and customer teams, represents the company at PCI-SIG, supports technical presales and customer solutions, develops patents and publications, and trains field teams.

Develop test plans and coverage for semiconductor products, design ATE hardware for new product introduction, and support products through prototyping, high-volume manufacturing, and sustaining operations. Optimize yield, test time, and multisite testing while collaborating with design teams, customers, suppliers, and offshore OSAT partners. The role requires expertise with Advantest V93k and familiarity with DFT methodologies, Smartest, Red Hat, and version-control tools.

Leads signal and power integrity modeling, simulation, package design, and system-level analysis for high-speed DDR memory products. Defines packaging, PCB routing, decoupling, channel, jitter, and SI/PI requirements; correlates simulations with laboratory measurements; supports debugging and product bring-up; collaborates with design, validation, customers, and cross-functional teams to optimize performance.

Lead semiconductor product engineering for new product introductions from kickoff through production and sustaining support. Define test coverage, characterization, qualification, schedules, and resources; coordinate cross-functional teams, customers, suppliers, foundries, and OSAT partners. Support wafer sort, final test, failure analysis, RMA activities, yield and quality optimization, and high-volume manufacturing. Apply expertise in analog, mixed-signal, power, DDR, and high-speed digital products, along with C/C++, Linux, ATE, and data-analysis tools.

Designs and architects next-generation PCIe intellectual property, develops RTL in Verilog and SystemVerilog, collaborates with verification teams, prototypes designs on FPGAs, and supports existing IP generations. The role requires advanced electrical or computer engineering education, extensive RTL design experience, strong communication skills, and preferably knowledge of PCIe or CXL standards.

Develops and executes growth plans for strategic semiconductor and silicon IP accounts. The role owns revenue, gross margin, design-win, forecasting, account expansion, and new-account acquisition goals. It builds senior customer relationships, assesses market opportunities, partners with marketing and business units on account strategies, identifies customer and market requirements, and supports new product launches.

Leads sales growth for Rambus Interface IP and Security businesses by managing strategic customer accounts, achieving revenue and design-win targets, forecasting demand, developing account strategies, identifying market opportunities, and building senior-level customer relationships. Partners with marketing and business units to align product launches, customer requirements, investments, and business development initiatives.

Designs, architects, simulates, and characterizes high-performance analog and mixed-signal circuits for DDR memory interface chips. Responsibilities include receiver and sampler design, modeling, voltage and timing analysis, analog layout supervision, cross-functional collaboration, post-silicon debugging, and silicon-to-simulation correlation.

Leads technical marketing for Rambus memory interface chip products, including product positioning, requirements development, technical collateral, ecosystem enablement, standards engagement, customer communications, training, and competitive analysis. Serves as the technical liaison among engineering, product management, sales, customers, processor vendors, SoC companies, memory suppliers, and industry partners. Supports product launches, qualification activities, customer issue resolution, and evaluation of future memory technologies such as DDR6 and MRDIMM.