Principal PCIe Logic Design

Posted 6 Days Ago
Be an Early Applicant
Hillsboro, OR, USA
Hybrid
108K-201K Annually
Senior level
Big Data • Internet of Things • Software
The Role
Designs and architects next-generation PCIe intellectual property, develops RTL in Verilog and SystemVerilog, collaborates with verification teams, prototypes designs on FPGAs, and supports existing IP generations. The role requires advanced electrical or computer engineering education, extensive RTL design experience, strong communication skills, and preferably knowledge of PCIe or CXL standards.
Summary Generated by Built In
Overview

Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.


This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues.


Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.  


Responsibilities
  • Contribute to the architecture and micro-architecture of next generation PCIe IP 
  • Implement these designs in System Verilog 
  • Collaborate with the verification team to verify the IPs 
  • Participate in prototyping of the IPs in cutting edge FPGAs 
  • Contribute to support of existing generations of the IPs 
Qualifications

Required:

  • RTL coding: Verilog / System Verilog
  • Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
  • 8+ years of experience with RTL Design
  • Good English skills, communication skills, and willingness to work with an international team. 

Additional Desirable skills:

  • Knowledge of PCIe / CXL

About Rambus 

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.  


Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.  


The US salary range for this full-time position is $108,300 to $201,100. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. 


At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work. 

 Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.  

  

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application. 


Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. 


For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. 


#LI-HYBRID

#LI-RF1

Skills Required

  • Verilog and SystemVerilog RTL coding experience
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or equivalent
  • 8 or more years of RTL design experience
  • Good English and communication skills
  • Willingness to work with an international team
  • Knowledge of PCIe or CXL
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The Company
HQ: San Jose, CA
989 Employees

What We Do

Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our architecture licenses, IP cores, chips, software, and services span memory and interfaces, security, and emerging technologies to positively impact the modern world. We collaborate with the industry, partnering with leading chip and system designers, foundries, and service providers. Integrated into tens of billions of devices and systems, our products and technologies power and secure diverse applications, including Big Data, Internet of Things (IoT) security and much more!

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