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Designs microarchitecture and RTL for high-performance memory controllers and critical logic blocks. Analyzes performance, power, and area trade-offs; collaborates with verification and physical design teams; debugs regressions; resolves timing and congestion issues; and supports field applications and customer deliveries. Requires extensive ASIC or FPGA logic design experience, strong SystemVerilog/Verilog skills, simulator and scripting experience, and the ability to work independently.

Develops and supports pre-silicon RTL verification for DRAM controller IP using SystemVerilog, UVM, testbenches, functional coverage, regression testing, scripting, and debug. Responsibilities include creating test sequences, monitoring and triaging regressions, correcting verification environments and RTL issues, and supporting controller technologies such as DDR, LPDDR, HBM, and GDDR. The role is intended for a junior engineer or recent college graduate.

Leads semiconductor product programs from concept through mass production, owning schedules, budgets, risks, resources, customer activities, product costs, quality, and program reviews. Partners with engineering and customers to deliver IC products on time and within specification and budget. Presents program status to executives, manages lifecycle exit reviews, coordinates engineering and customer samples, and drives alignment across matrixed teams.

Reviews and processes customer purchase orders, validates commercial terms and billing details, coordinates order issue resolution, and manages order-to-cash activities. Maintains records for compliance, supports backlog and fulfillment reporting, analyzes sales and revenue data, and develops Power BI, Excel, and ERP dashboards. Drives process improvements across forecasting, reporting, and sales operations workflows while collaborating with Sales, Finance, Legal, Operations, and Customer Service.

Develop and validate bench and system environments for DDR5 enablement devices, ensuring performance specification compliance. Responsibilities include characterizing I2C/I3C protocols, automating laboratory testing with Python, supporting customers, and providing post-silicon bring-up support while coordinating with design, operations, and development teams.

Lead microarchitecture and RTL design for high-performance memory controller blocks. Analyze power, performance, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and timing, power, and congestion issues; and support customer pre-sales and post-sales engagements.

Own microarchitecture and RTL design for high-performance memory controller blocks. Analyze performance, power, and area tradeoffs; collaborate with verification and physical design teams; debug regressions and resolve timing, power, and congestion issues. Provide technical support for pre-sales customer engagements and post-sales deliveries. The role requires extensive ASIC/FPGA logic design experience and expertise in SystemVerilog or Verilog, simulation tools, and scripting.

Designs microarchitecture and RTL for high-performance memory controller blocks, analyzes performance, power, and area trade-offs, collaborates with verification and physical design teams, debugs regression failures, and supports customer engagements. The role requires extensive ASIC or FPGA logic design expertise, simulator and scripting experience, and offers opportunities to work with advanced memory technologies and interfaces.

Develops pre-silicon RTL verification for memory controller IP supporting DDR, HBM, and GDDR technologies. Responsibilities include testbench and test-sequence development, functional coverage planning, regression testing, debug and triage, RTL issue analysis, and verification-environment scripting. The role requires expertise in SystemVerilog and Verilog, with Python and Tcl scripting preferred, plus substantial design-verification experience.

Designs and implements SystemVerilog and Verilog RTL for DDR5 and DDR6 memory interface products. Responsibilities include block integration, simulation, PPA analysis, timing improvement, functional modeling, design quality checks, verification debugging, documentation, and chip power-on validation. Collaborates with digital, analog, physical design, verification, validation, and product qualification teams.