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Drive SoC and server platform performance by characterizing real-world AI/HPC workloads on production silicon, designing microbenchmarks, diagnosing bottlenecks, and translating findings into architectural and system-level optimizations while collaborating with hardware and software teams.

The Principal High-Speed I/O Architect designs interconnect architectures for SoCs, collaborating on performance and efficiency in various markets.

Lead workload and silicon-level performance analysis for next-generation server platforms (AI at scale and HPC). Define metrics and benchmarks, build microbenchmarks, identify bottlenecks, recommend architectural optimizations, and collaborate with hardware and software teams to validate improvements end-to-end.

Lead security architecture and the Secure Development Lifecycle (SDL) for Arm SoC and hardware security IP. Define SoC Root of Trust, Secure Boot, key management, confidentiality and access controls; perform threat modeling and derive security functional requirements. Own SDL process, produce security artifacts, drive V&V plans, support certifications (PSA, FIPS, ISO/SAE), mentor teams, and ensure security verification from concept through post-silicon delivery.

Architect and design high-volume SoC platforms using Arm IP across mobile, automotive, datacenter, networking and IoT. Lead cross-functional teams to define platform architecture, optimize performance and power, coordinate IP delivery, drive partner engagements, and influence roadmap and feature development. Guide specification maturity and ensure on-time delivery while driving innovation and continuous improvement.

The SoC RAS Architect drives reliability and serviceability strategies for SoCs, ensuring compliance with data center standards through collaboration with design and engineering teams.

Lead full-chip and block-level timing closure for complex SoCs across project lifecycle. Define and manage timing constraints, collaborate with cross-functional teams and EDA vendors, perform ECOs, address timing for multiple power domains and advanced nodes (5nm/3nm), and automate flows using scripting.

Lead end-to-end execution of complex multi-die SoC programs, coordinating Die and Functional TPMs, managing schedule, risks, tapeout readiness, cross-die integration, metrics, governance reviews, and program budgets to ensure on-time, on-quality delivery.

Lead customer success and program management for strategic hyperscaler accounts, coordinating Arm engineering, product, and ecosystem partners to drive adoption of Arm technologies across silicon, platforms, and cloud infrastructure. Own success plans, program dashboards, governance, executive reviews, risk mitigation, and cross-functional delivery while advocating customer needs and identifying opportunities for expanded adoption.

Provide technical mentorship and support to partners integrating Arm CPUs and System IP into SoCs. Perform RTL simulation-based debugging, SoC build reviews, deliver training, influence IP development, test IP, and create knowledge-base content and tooling to improve partner outcomes.