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Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
137K-254K Annually
Senior level
137K-254K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Principal Product Engineer will develop and drive customer adoption of AI-driven Layout Automation flows, focusing on analog layout expertise and automation technology, while collaborating with customers.
Top Skills: Analog LayoutLayout AutomationScriptingVirtuoso Custom Design Platform
Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
137K-254K Annually
Senior level
137K-254K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Develop and maintain EDA tools for transistor-level analysis. Enhance architecture for timing analysis and implement machine learning technologies for improved solutions.
Top Skills: C++LinuxSpiceUnix
Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
137K-254K Annually
Senior level
137K-254K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Datacenter Operations Manager oversees 24x7 data center operations, ensuring IT infrastructure availability, reliability, and integrity, while managing infrastructure deployments and SLA compliance.
Top Skills: It InfrastructureLinuxNetworkingUnix
Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
179K-332K Annually
Expert/Leader
179K-332K Annually
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The ATE Test Engineering Architect will lead the development of production test solutions for complex SoCs, including test strategy, execution, yield analysis, and mentoring engineers.
Top Skills: Advantest 93K Ate PlatformAte Test DevelopmentDft
Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
137K-254K Annually
Senior level
137K-254K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Drive development and customer adoption of Analog Design automation flows in Virtuoso, optimizing and enhancing customer design workflows and methodologies.
Top Skills: Ai Driven OptimizationAnalog/Mixed-Signal Circuit DesignLayout-Driven Design MethodologiesParasitic-Aware DesignPythonSkillVirtuoso
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Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
115K-213K Annually
Mid level
115K-213K Annually
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Serve as a technical evangelist for Cadence analog design tools and agentic workflows. Demonstrate product capabilities to customers, resolve customer issues with application engineers, advocate customer needs to R&D, and help define improved use models and user interfaces to advance analog/RF/mixed-signal circuit design workflows.
Top Skills: Agentic WorkflowsAi AgentsCadence Virtuoso AdeGenerative AiLlmsRag (Retrieval-Augmented Generation)Shell ScriptingSkill
Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
133K-247K Annually
Expert/Leader
133K-247K Annually
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Infrastructure Architect will lead M&A infrastructure integration efforts, ensuring minimal disruption while optimizing systems and networking across merged environments.
Top Skills: LinuxNasNutanixSanUnixVMwareWindows Server
Reposted 18 Days AgoSaved
In-Office
San Jose, CA, USA
102K-189K Annually
Mid level
102K-189K Annually
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Develop AI/ML technologies and tools to accelerate standard-cell library characterization. Build infrastructure for characterization data mining and model library cells for aging and variation effects. Maintain and enhance C++ applications on Unix/Linux, design data structures and algorithms, and follow software quality and engineering processes.
Top Skills: Ai/MlC++EdaLiberateLinuxUnix
Reposted 20 Days AgoSaved
In-Office
San Jose, CA, USA
179K-332K Annually
Senior level
179K-332K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Design and build scalable EDA flows and AI/LLM-driven automation for 3DIC, interposer, and RDL systems. Implement flow-generation, debugging assistants, root-cause analysis, and platform integration using C++, Tcl, Python, and Java. Collaborate with engineering teams to validate flows, automate constraint-driven designs, and address large-scale, high bump-count and multi-region routing challenges to deliver production-quality solutions.
Top Skills: 3DicAIC++DrcEdaInnovusInterposerJavaLlmPythonRdlSignal IntegrityTclTiming
Reposted 20 Days AgoSaved
In-Office
Austin, TX, USA
Senior level
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
Lead Front End Design projects, mentoring RTL engineers, define IP features, write and optimize RTL code, oversee pre-silicon verification, and collaborate with cross-functional teams.
Top Skills: SystemverilogVerilogVhdl
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