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Provide technical support in backend digital design, involving Place and Route and timing/power signoff, while guiding customers on Cadence technologies and improving methodologies.

Drive product engineering for Cadence Genus synthesis solution to improve Power, Performance & Area. Verify new features, perform experiments, debug physical-aware synthesis issues, and ensure interoperability with other Cadence tools. Support field engineers and customers, document product requirements, and bridge synthesis with place-and-route flows.

Entry-level, cohort-based rotational role providing front-line EDA application support, technical sales assistance, and design services. Work with customers and internal teams on digital/analog design, verification, simulation, physical design, timing/power/SI sign-off, embedded HW/SW co-verification, and hardware emulation. Two six-month technical rotations followed by placement in a CST business group.

Customer-facing senior technical account leader who defines and executes account technical strategies for the Cadence SVG platform. Acts as trusted advisor, communicates customer needs to internal teams (AE, R&D, business unit), drives technical campaigns globally, and owns all customer interactions for strategic accounts.

Embed with strategic semiconductor customers to deploy LLM- and agent-based AI into end-to-end EDA flows (RTL through signoff). Architect agentic workflows, integrate Cadence AI products, define KPIs for productivity and ROI, guide secure LLM access and infrastructure, run design reviews, and produce reusable playbooks to scale deployments across sites.

Lead a worldwide account team to drive adoption and growth of Cadence solutions. Build sales pipeline, consult with executive customers on design/system requirements, architect solutions using EDA software, IP, hardware and services, and advocate customer needs across Cadence to ensure long-term success and roadmap alignment.

Lead development and support of chip power integrity, IR, and EM analysis tools and workflows. Solve electrical circuit and numerical/graph algorithm problems, model interconnects, package and die, write automation in Python/Tcl, and collaborate with EDA and semiconductor teams to drive IR/EM sign-off solutions.

Provide strategic technical leadership bridging quantum, photonics, and EDA by engaging customers, defining high-impact Cadence-based solutions, shaping project scope and requirements, and partnering with services and R&D to influence tool and methodology development and drive execution.

Internship in software engineering focused on developing leaders and innovators in technology at Cadence.

You will design and implement high-performance software while applying machine learning techniques to complex problems in electronic design automation.