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Drive development and customer adoption of advanced backend custom IC design flows in Cadence Virtuoso for advanced nodes. Provide customer-facing support: troubleshoot issues, create automation and scripts, collaborate with R&D, and deliver documentation and training to enable efficient layout and signoff flows.

You will design and implement high-performance software while applying machine learning techniques to complex problems in electronic design automation.

Lead software engineer responsible for designing high-level and detailed architectures, performance tuning, and building distributed systems. Work with LLM/ML and big-data technologies (e.g., Langchain, Spark), develop in Python and C++, and design data solutions with strong SQL and database fundamentals. Collaborate across teams and integrate diverse frameworks into practical solutions.

Lead a worldwide account team to drive adoption and growth of Cadence solutions. Build sales pipeline, consult with executive customers on design/system requirements, architect solutions using EDA software, IP, hardware and services, and advocate customer needs across Cadence to ensure long-term success and roadmap alignment.

Entry-level, cohort-based rotational role providing front-line EDA application support, technical sales assistance, and design services. Work with customers and internal teams on digital/analog design, verification, simulation, physical design, timing/power/SI sign-off, embedded HW/SW co-verification, and hardware emulation. Two six-month technical rotations followed by placement in a CST business group.

Drive product engineering for Cadence Genus synthesis solution to improve Power, Performance & Area. Verify new features, perform experiments, debug physical-aware synthesis issues, and ensure interoperability with other Cadence tools. Support field engineers and customers, document product requirements, and bridge synthesis with place-and-route flows.

Embed with strategic semiconductor customers to deploy LLM- and agent-based AI into end-to-end EDA flows (RTL through signoff). Architect agentic workflows, integrate Cadence AI products, define KPIs for productivity and ROI, guide secure LLM access and infrastructure, run design reviews, and produce reusable playbooks to scale deployments across sites.

Design and develop analog/mixed-signal IC blocks for high-speed SerDes from concept through verification. Responsibilities include circuit design (drivers, receivers, serializers/deserializers, PLLs, ADC/DACs, biasing, regulators), simulation and layout using CAD tools, lab testing, and collaboration with cross-functional teams.

Prepare quarter-end reporting and audit committee deliverables, validate finance data from SAP/Incorta/CPM/NGA, generate reports and ad hoc analyses, perform data quality reviews and reclasses, support UAT and system enhancements, assist acquisition integrations, and partner with quote-to-cash and cross-functional teams to resolve reporting discrepancies.

Lead design and implementation of the SystemVerilog compiler and code generator for Xcelium, optimize front-end and codegen for multi-billion gate designs, perform performance engineering in C++, and prototype innovations like LLM-enhanced, parallel, and distributed compilation.