Lead Customer Engagement Engineer

Posted 23 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
119K-221K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Provides technical support for Cadence Palladium, Protium, and Virtual Protocol products. Responsibilities include debugging customer failures, creating replication test cases, coordinating issues with R&D, recommending workarounds, testing fixes and patches, specifying enhancements, and validating new hardware and software features. The role requires expertise in digital design verification, HDL, Unix/Linux scripting, hardware protocols, emulation, and customer communication, with occasional travel.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As an integral member of the HSV Customer Support Team, you will work with our customers and field AE teams and R&D groups to provide technical support for our Palladium, Protium and Virtual Protocol (PDAPP) products. You will enjoy the experience and challenge in working with a broad spectrum of designs and customers.


Responsibilities includes: 

  • Taking ownership and quickly drive to resolution product issues reported by field AEs and customers.
  • Debug customer reported failures, produce test cases to replicate failure and log issues with HSV R&D teams.
  • Recommend potential workaround or application level solutions to customers when necessary.
  • Test R&D fixes/patches.
  • Work with customer and internal groups to spec out enhancement requests.
  • Testing new product features for future s/w releases or h/w platform, including participation in internal beta activities.

Position Requirements:

  • Requires a BS-EE/CE (MS-EE/CE preferred) with a minimum of 5 years experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
  • Strong knowledge of design debug techniques and a strong understanding in logic design.
  • Knowledgeable in verification methodologies for complex EDA environments.
  • Proficiency in HDL language like Verilog, System Verilog and VHDL. Ability to create test cases to replicate customer issues quickly.
  • Proficiency in Unix/Linux scripting languages (ksh/bash/csh).
  • Proficiency in PCIe, USB and Ethernet protocol.
  • Proficiency in TBA, SVA, SV coverage, Low Power(UPF). UVM experience is a plus.
  • Experience with emulation, Cadence's Palladium product preferred.
  • Excellent communication skills.  Must have ability to communicate complex issue to internal teams and customers in a clear and concise manner.
  • Occasional travel may be required to resolve critical customer issues.

The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor’s degree in Electrical Engineering or Computer Engineering
  • At least 5 years of experience in complex digital design, design verification, applications engineering, or technical support
  • Strong knowledge of design debugging techniques and logic design
  • Knowledge of verification methodologies for complex EDA environments
  • Proficiency in Verilog, SystemVerilog, and VHDL
  • Ability to create test cases to quickly reproduce customer issues
  • Proficiency in Unix/Linux shell scripting, including ksh, bash, or csh
  • Proficiency in PCIe, USB, and Ethernet protocols
  • Proficiency in TBA, SVA, SV coverage, and low-power UPF
  • Excellent communication skills and ability to explain complex issues clearly
  • Master’s degree in Electrical Engineering or Computer Engineering
  • UVM experience
  • Experience with hardware emulation and Cadence Palladium

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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