The Cadence Palladium Platform is world most scalable emulation system that verifies most of the latest design innovations in electronics worldwide. We are looking for a talented engineer to join our team and contribute to the world’s fastest emulator compiler development. You’ll have a great opportunity to make a difference by applying your creativity and problem-solving skills, learn and/or apply multi-threading/distributed computing to solve large scale compile problems such logic optimization, distributed database and precompiler techologies.
Strong understanding of software data structure and algorithms and proficiency in C/C++ are basic job requirements.
Requirements
- MS. With 2 year experience or Ph.D in engineering, computer science or related field.
- Strong understanding of data structures, algorithms and databases.
- Demonstrated proficiency in C++, gdb debugging, and general software development skills
- Familiarity with Linux/Unix development.
- Exposure to build and version-control systems.
- Coursework in Hardware Descript Language, such as Verilog, SystemVerilog, VHDL.
- Exposure to electronic design platforms.
The annual salary range for Massachusetts is $101,500 to $188,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Master’s degree in engineering, computer science, or a related field with at least two years of experience
- Ph.D. in engineering, computer science, or a related field
- Strong understanding of data structures, algorithms, and databases
- Proficiency in C++
- Experience with GDB debugging
- General software development skills
- Familiarity with Linux/Unix development
- Exposure to build and version-control systems
- Coursework in a hardware description language such as Verilog, SystemVerilog, or VHDL
- Exposure to electronic design platforms
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
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