Top Tech Jobs & Startup Jobs

Lead an R&D team developing C++ software and AI/ML technologies for static and dynamic transistor-level analysis and characterization of advanced digital and mixed-signal circuits. Responsibilities include building characterization data-mining infrastructure, modeling aging and variation effects in advanced technology nodes, and applying data structures, algorithms, and software engineering practices to improve analysis speed, capacity, and usability.

Drives customer engagements, partners with Field Applications and R&D teams, influences product development, manages beta programs, documents products, and tracks customer issues. The role requires expertise in IC design, passive components, signal and power integrity, analysis, and 3D computational electromagnetics, along with scripting and Linux command-line experience.

Develops and delivers software integrations and design-analysis flows for package and PCB electromagnetic analysis. The role evaluates and resolves complex customer issues, qualifies defects, benchmarks tools, improves product performance, and coordinates requirements and enhancements with customers, foundries, R&D, marketing, and global product engineering teams.

Leads ASIC design services and silicon fulfillment sales, owning bookings, revenue, pipeline, forecasting, and strategic customer engagements. Manages senior sales professionals, coaches deal execution, negotiates complex contracts, and collaborates with delivery, R&D, IP, EDA, foundry, and ecosystem teams. Guides proposals, pricing, opportunity qualification, resource allocation, and risk management while influencing go-to-market strategy and customer satisfaction.

Leads software release management for Cadence sign-off products, coordinating R&D, validation, configuration management, and product engineering teams. Defines release scope, tracks milestones, monitors progress and quality metrics, removes bottlenecks, and improves software development and deployment processes. The role requires extensive program management experience, software development and validation knowledge, cross-functional leadership, strategic planning, and risk management. EDA expertise and Python, C, or C++ programming experience are preferred.

Develop and optimize high-performance, multi-threaded software for physical synthesis and routing in digital IC design. Responsibilities include algorithm research, C/C++ development on Linux, distributed-system debugging, performance optimization, and collaboration with global R&D and product engineering teams. The role supports advanced semiconductor design flows and may involve GPU programming, scripting automation, timing analysis, and EDA tools.

Staff Financial Analyst supporting commissions operations by improving processes, automating workflows, reducing financial reporting risk, and collaborating with Sales Operations. The role requires commissions systems experience, finance data extraction and reporting knowledge, advanced Excel skills, strong analytical ability, and attention to detail. Preferred experience includes sales compensation operations, ASC 606 revenue accounting, and process automation.

Develops, enhances, tests, troubleshoots, and documents software throughout the development lifecycle. Reviews code, resolves defects, translates technical requirements into scalable solutions, and contributes to system architecture and development-process improvements. Requires substantial C++ experience, desktop engineering and OpenGL expertise, computational geometry knowledge, cross-platform development experience, and the ability to handle ITAR-controlled data. Relocation to Austin, Texas may be required.

Designs high-performance analog and mixed-signal IC layouts from floor planning through detailed layout and physical verification. Collaborates with circuit designers, global layout teams, and Cadence R&D to deliver CMOS IP and test chips across advanced process nodes. Applies analog layout techniques including matching and shielding while considering speed, capacitance, power, and area. Uses Cadence Virtuoso and physical verification tools.

Leads customer and partner engagements for Cadence timing signoff and closure solutions across advanced semiconductor nodes. Drives STA, IR Drop, power and timing closure benchmarks, flow optimization, tool adoption, and methodology deployment. Collaborates with R&D and product engineering, influences tool enhancements, leads technical programs, and represents Cadence through industry presentations and technical publications. Requires deep advanced-node signoff expertise, scripting skills, customer leadership, and familiarity with Cadence EDA tools.