Application Engineer Architect (STA SignOff)

Posted 2 Days Ago
Be an Early Applicant
7 Locations
In-Office
154K-286K Annually
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Leads customer and partner engagements for Cadence timing signoff and closure solutions across advanced semiconductor nodes. Drives STA, IR Drop, power and timing closure benchmarks, flow optimization, tool adoption, and methodology deployment. Collaborates with R&D and product engineering, influences tool enhancements, leads technical programs, and represents Cadence through industry presentations and technical publications. Requires deep advanced-node signoff expertise, scripting skills, customer leadership, and familiarity with Cadence EDA tools.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

  • Technical Expertise: Lead technical engagements with customers and partners to drive & adoption of Cadence signoff portfolio. Work closely with design teams to meet customer success metrics, guide adoption of Cadence’s timing signoff & closure and AgenticAI features across advanced nodes (5nm and below).
  • Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
  • Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for timing sigoff & closure, STA, IR Drop, and power/timing closure.
  • Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.

Qualifications

  • 15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
  • BS/MS in Electrical Engineering, Computer Engineering, or related field.
  • Deep expertise in digital design fundamentals, advanced node STA & ECOs (3nm and below), and EDA tool ecosystems.
  • Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
  • Proven track record of leading technical teams and driving customer success at executive levels.
  • Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
  • Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
  • Prior experience with Cadence tools (Tempus, Certus, QRC) and competitive solutions highly desirable.

The annual salary range for Washington is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

Skills Required

  • 15+ years of experience in IC design implementation and signoff
  • Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • Deep expertise in digital design fundamentals, advanced-node STA and ECOs
  • Expertise in timing signoff, advanced-node STA, UPF and constraints debugging, hierarchical and 3DIC STA, and closure solutions
  • Experience managing large-scale technical programs
  • Track record of leading technical teams and driving executive-level customer success
  • Proficiency in Tcl, Python, and Perl scripting for design-closure flow customization
  • Excellent communication, negotiation, leadership, and stakeholder-influence skills
  • Prior experience with Cadence Tempus, Certus, QRC, and competitive solutions

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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