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Leads business strategy and account growth for Cadence’s EDA software, hardware, services, and IP portfolio. Manages strategic customer relationships, pre- and post-sales campaigns, forecasting, quoting, negotiation, and deal closure. Coordinates worldwide sales and field resources while aligning customer technical roadmaps with Cadence solutions. Requires strong EDA expertise, executive communication, negotiation, cross-functional collaboration, and an 8+ year track record in a related field.

Leads R&D development projects and key customer engagements for mixed-signal design IP. Responsibilities include defining scope and deliverables, tracking and reporting progress, resolving project issues, managing customer relationships, and coordinating Sales, Marketing, Finance, and Engineering in a matrix organization. Requires experience with mixed-signal design or SoC development, end-to-end analog and digital design flows, and managing teams from conception through manufacturing.

Design and implement SoC-level design-for-test architecture for complex chip designs. Responsibilities include SCAN, ATPG, MBIST, BSCAN, and iJTAG integration; DFT insertion and verification; coverage analysis; pre-silicon sign-off and DRC closure; post-silicon debug, failure analysis, and yield learning. The role collaborates with RTL, verification, physical design, and operations teams, with scripting and low-power DFT experience preferred.

Lead program management for HSV product releases, coordinating scope, milestones, delivery, interoperability, validation, configuration management, engineering, marketing, support, and documentation teams. Monitor release progress and quality metrics, remove bottlenecks, improve processes, and drive operational excellence. The role requires cross-functional leadership, strategic planning, risk and change management, people management, and expertise in software development and validation processes within fast-moving agile environments.

Leads implementation and verification of Palladium and Protium SoCs through tapeout. Responsibilities include RTL synthesis, floorplanning, clock-tree construction, timing closure, IR-drop analysis, physical verification, design documentation, and collaboration with frontend RTL and backend verification teams. The role requires expertise with Cadence physical design tools, advanced semiconductor nodes, Linux-based scripting, and industry-standard interfaces.

The Design Engineering Architect role at Cadence involves designing innovative technology solutions and leading projects that impact technology.

Three-month summer internship supporting physical system design and analysis using CAE tools, simulation workflows, Python scripting, and AI applications. The intern will assist with engineering analysis, data processing, reporting, professional services, project delivery, and customer-ready technical outputs while collaborating with application engineers and technical experts.

Entry-level application engineering role for recent engineering graduates in a cohort-based development program. Participants rotate through technical sales, customer support, training, and professional services while using Cadence CAE tools for physical-system simulation and analysis. Responsibilities include coding and scripting with Python, troubleshooting customer problems, developing solutions and demonstrations, supporting projects, creating engineering outputs, and applying artificial intelligence to engineering workflows and customer service.

Provides expert field applications engineering support for Cadence digital implementation and signoff technologies. Guides customers through synthesis, place and route, design closure, timing and power signoff, technical evaluations, demonstrations, and tool adoption. Collaborates with R&D to improve products and methodologies, develops Tcl or other scripts to optimize design flows, and shares best practices. Requires extensive physical design experience, advanced-node expertise, semiconductor and timing knowledge, scripting skills, and strong customer communication.

Entry-level rotational application engineering role for new STEM bachelor’s graduates. Provides customer-facing design services, technical sales support, and troubleshooting for Cadence EDA tools. The one-year program includes rotations across digital, physical, analog, package, systems, verification, and emulation design, with training in HDLs, synthesis, UNIX, programming, scripting, and silicon analysis. Graduates transition into a permanent CST business group based on interests and company needs.