Sr. Principal IC Digital Flow AE

Posted Yesterday
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San Jose, CA, USA
In-Office
148K-276K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Provides expert field applications engineering support for Cadence digital implementation and signoff technologies. Guides customers through synthesis, place and route, design closure, timing and power signoff, technical evaluations, demonstrations, and tool adoption. Collaborates with R&D to improve products and methodologies, develops Tcl or other scripts to optimize design flows, and shares best practices. Requires extensive physical design experience, advanced-node expertise, semiconductor and timing knowledge, scripting skills, and strong customer communication.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As an expert Digital Implementation and Signoff Field Applications Engineering (AE) , you will work side-by-side with our leading edge customers. With your expertise, you'll help them deploy Cadence’s market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. The greater your powers, the more business opportunities you'll help bring to the table. You will also work directly with the Cadence R&D group to drive the customer requirements and influence the direction of Cadence next-generation products and technologies.

At Cadence, customers are at the heart of everything we do. Talented leaders like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills.

Key Responsibilities

  • Be part of  team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff
  • Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
  • Collaborate with team to conduct technical presentations and product demonstrations
  • Drive technical evaluations/benchmarks to success
  • Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
  • Drive adoption and proliferation of Cadence tools and technologies 
  • Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
  • Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements 

Job Requirements

Minimum

  • 10+ years of industry Physical Design experience
  • BS degree Computer Science/Engineering, Electrical, Engineering, or related field
  • Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required
  • Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure
  • Experience with advanced nodes 10nm and below
  • Experience in scripting languages such as Tcl/Perl/Python is a must
  • Strong customer-facing communication and problem-solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Strong verbal, written, and customer communication skills

Preferred

  • MS degree Computer Science/Engineering, Electrical, Engineering, or related field
  • Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
  • Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired
  • Experience with advanced nodes 5nm and below

The annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 10+ years of industry physical design experience
  • Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field
  • Strong knowledge of digital design fundamentals, semiconductor fundamentals, and static timing analysis
  • Experience with IC digital implementation flows and backend EDA tools, including place and route, IR drop, backend timing, and power closure
  • Experience with advanced semiconductor nodes of 10nm and below
  • Experience with Tcl, Perl, or Python scripting
  • Strong customer-facing communication and problem-solving skills
  • Strong drive for continuous learning and professional development
  • Strong verbal, written, and customer communication skills
  • Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field
  • Experience with front-end EDA tools and flows, including synthesis, DFT, and logical equivalence checking
  • Experience with Cadence Genus, Innovus, Conformal, Tempus, Modus, Voltus, or competing tools such as ICC, ICC2, Design Compiler, or PrimeTime
  • Experience with advanced semiconductor nodes of 5nm and below

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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