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Principal Applications Engineer for Cadence Serdes IP: define and architect high-speed interface solutions (PCIe, CXL, Ethernet, USB), demonstrate IP performance, lead technical presales, support customers, collaborate with sales/R&D/marketing, produce application notes, and drive process improvements. Occasional travel to customer sites and events.

Designs and develops mixed-signal physical IP for high-speed serial links, from architectural specifications through circuit design, verification, post-silicon testing, and functional/performance closure. Collaborates with digital engineering teams, contributes to project leadership, develops test plans, and performs silicon validation. The role requires expertise in mixed-signal design fundamentals, verification flows, Cadence tools, and signal processing, with experience in advanced process technologies.

Designs, verifies, productizes, maintains, and supports system-level memory IP models for hardware-based verification platforms. Develops RTL using Verilog/SystemVerilog across memory technologies and interfaces, executes simulation and emulation verification, debugs complex hardware and protocol issues, documents products, supports customers, manages technical deliverables, and collaborates across engineering teams to improve product quality and lifecycle processes.

Contribute to EDA software for advanced PCB design, including Agentic AI-supported PCB generation. Help develop product requirement specifications by analyzing input from technical stakeholders, customers, and colleagues. Provide development teams with feedback on layout-tool functionality, user experience, and use models. The internship requires onsite, full-time work in Burlington during Fall 2026.

Manage a portfolio of Bay Area strategic accounts to drive multi-million-dollar bookings. Build C-level relationships, develop multi-year account strategies, lead complex, multi-stakeholder sales cycles, coordinate cross-functional teams, and expand revenue across Cadence software, hardware, IP, verification, system design and AI-driven solutions.

Lead and manage M&A and strategic investment transactions end-to-end, provide strategic legal advice to senior management, oversee due diligence, negotiate complex agreements, manage post-investment matters and external counsel, ensure regulatory compliance, and develop playbooks and integration processes.

The Product Marketing Manager will lead product strategy and go-to-market execution for Tensilica IP, focusing on customer engagement, market opportunities, and future product requirements.

Responsible for designing and scaling supply chain strategies, managing supplier relationships, negotiating contracts, and advising on procurement strategies for operational performance.

The Principal Product Engineer focuses on delivering emulation and virtual protocols for SOC verification, collaborating with R&D and customers to implement product features and ensure readiness for deployment.

The Software Intern at Cadence will work on research and development using machine learning technologies for on-chip parasitic modeling in a team environment.