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The ASIC Design Efficiency Engineer will develop innovative hardware and system designs, focusing on performance, power, and area improvements, while collaborating with cross-functional teams.

Lead DFT methodology and IP design for SoC products, owning fuse controller architecture, RTL development, verification, and full-chip test plans. Collaborate with cross-functional teams for integration, support post-silicon bring-up and ATE validation, debug failures, and mentor junior engineers.

Design and implement CUDA/C++ libraries to accelerate Apache Spark DataFrame and I/O operations, collaborate on distributed multi-node GPU solutions, contribute to open-source projects (RAPIDS, CCCL, UCX), and drive testing, CI, and cross-platform optimization for enterprise deployments.

Partner with architecture and design teams to plan and execute functional and performance verification for GPU memory subsystem IP. Develop testbenches, BFMs, monitors and regressions, close coverage, enable FPGA/software testing, and support post-silicon verification and debug to sign off RTL.

Lead product definition, execution, and go-to-market for AI physics models, libraries, and frameworks. Collaborate with engineering, developer relations, marketing, and sales; present to internal and external audiences; prioritize projects; translate technical capabilities into developer and customer value.

Lead developer relations and research partnerships in 6G and AI-native RAN. Conduct simulations, design and code AI/ML and LLM algorithms for RAN, publish papers and IP, engage 3GPP and AI-RAN bodies, and collaborate with cross-functional teams to drive accelerated-computing solutions.

Lead developer relations for NVIDIA's local AI ecosystem: manage strategic partner portfolio, provide technical guidance, drive adoption of NVIDIA accelerated computing and runtimes, define joint plans and success metrics, enable partners with integrations and content, represent partner needs internally, and evangelize local AI at events.

Lead supply planning strategy for Boards and Systems products, develop scalable planning frameworks across components, ensure data integrity (BOM, yields, cycle times), accelerate time-to-market using advanced/AI planning, and manage global supply planning teams.

Lead cross-company image quality programs: gather requirements, build and drive project plans, manage risk and bug lifecycle, coordinate partners (OEMs, Tier1s, sensor/module suppliers), and apply GenAI to improve program processes while communicating status broadly.

Lead global GeForce esports and competitive gaming marketing: plan and execute campaigns, manage publisher and partner relationships, run product launch GTM and sponsorships, measure performance and optimize via analysis and dashboards.