Top Tech Jobs & Startup Jobs

Defines next-generation HBM PHY and analog/mixed-signal I/O architectures for high-bandwidth memory products. Responsibilities include transmit and receive path design, clocking, signaling, equalization, timing budgets, analog calibration, adaptive tuning, and silicon learning methodologies. The role leads cross-functional architectural decisions, evaluates performance, power, area, reliability, and manufacturability tradeoffs, drives roadmap innovation, develops engineering standards, and mentors design teams through concept-to-silicon execution.

Supports silicon bring-up, testing, and validation of new ASIC devices. Uses laboratory equipment, automation tools, and validation environments to characterize functionality and performance. Develops scripts and AI-assisted workflows, analyzes results, debugs issues, evaluates AI-generated insights, documents findings, and presents recommendations. Collaborates with validation, design verification, and firmware engineering teams while contributing to validation infrastructure and next-generation semiconductor product development.

Lead system-level signal and power integrity engineering for next-generation HBM products. Responsibilities include channel analysis for 2.5D and 3D interposers, power delivery architecture, electromagnetic modeling across PCB, package, and interposer designs, and establishing SI/PI standards and sign-off criteria. The role provides technical direction across complex designs and requires expertise in electromagnetics, transmission lines, I/O design, EDA tools, and automation scripting.

Lead the architecture and delivery of production AI, machine learning, data science, and agentic AI systems for semiconductor engineering. Design end-to-end pipelines, develop and evaluate models, deploy inference services, establish monitoring and guardrails, and guide technical roadmaps. Apply prediction, diagnosis, optimization, retrieval, and workflow automation to engineering challenges while mentoring engineers and communicating progress, risks, and model limitations to technical and executive stakeholders.

Develop, optimize, and sustain semiconductor fabrication processes to improve yield, quality, cost, and productivity. Use SPC/FDC/APC and data analytics to investigate defects, lead process changes, qualify technologies, manage process control plans, and collaborate across manufacturing, quality, and equipment teams.

Supports high-volume semiconductor manufacturing by monitoring and optimizing processes, improving yield and equipment efficiency, resolving process and equipment issues, analyzing manufacturing data, maintaining operational procedures, and implementing continuous improvements. The role requires rotating 12-hour shifts in a cleanroom environment and collaboration with equipment engineers, operations teams, and process owners.

Research and prototype memory and system architecture concepts for AI accelerators. Develop performance models, analyze AI and HPC workloads, evaluate memory hierarchy and interconnect optimizations, and assess bandwidth, latency, power, scalability, and system efficiency. Collaborate with cross-functional engineering teams and apply AI-based tools to architecture research.

Develops automated methodologies to resolve supply shortages, optimize semiconductor supply and inventory plans, analyze demand and shipment trends, and support capacity planning. The role uses operations research, statistical analysis, planning systems, and dashboards to improve supply fulfillment, inventory distribution, fab prioritization, and revenue-plan performance. It also evaluates inventory risks and collaborates with cross-functional stakeholders on resolution strategies.

Supports physical implementation of HBM SoC design blocks, including floorplanning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification. Analyzes timing, power, area, congestion, and signoff results while developing automation scripts and workflows using Python, Tcl, shell scripting, and AI-assisted tools. Collaborates with architecture, RTL, verification, DFT, and signoff teams on next-generation memory designs.

Supports advanced HBM DRAM design by interfacing with foundries, evaluating semiconductor technologies, performing HSPICE and circuit analyses, validating test chips and silicon, assessing PDKs, enabling design flows, and improving engineering productivity through AI and automation. The role requires expertise in advanced CMOS, FinFET devices, process integration, device characterization, PPA analysis, parasitic extraction, and physical verification, with collaboration across design, foundry, manufacturing, and product engineering teams.