Direct system-level Signal Integrity and Power Integrity architecture, analysis, simulation, and optimization for a next-generation MPU. The role covers high-speed serial and memory interfaces, including DDR5 and LPDDR, correlates simulations with lab measurements, resolves silicon-to-system integrity issues, and collaborates across silicon, package, PCB, architecture, and manufacturing teams. It also evaluates future package and PCB technologies and provides technical leadership and mentorship.

Leads end-to-end ASIC and SoC verification strategy, methodology, coverage closure, tape-out sign-off, and post-silicon bring-up. Architectures verification environments and test plans, reviews testbench code, debugs complex protocol and coverage issues, and presents readiness and risk metrics to engineering leadership. Recruits and develops the verification organization while managing technical risk, escalations, budget, and headcount. The role requires extensive hands-on verification experience, multiple advanced-node tapeouts, and high-speed protocol expertise.