Top Tech Jobs & Startup Jobs

YesterdaySaved
In-Office
Santa Clara, CA, USA
91K-120K Annually
Entry level
91K-120K Annually
Entry level
Semiconductor • Manufacturing
Owns assigned image sensor and ASIC products, contributes to product definition and DFM, leads product introduction and ramp-up, analyzes yield, drives corrective actions, finalizes datasheets through characterization, and collaborates with test engineers to develop, verify, and release wafer probe and final test programs.
Top Skills: AsicsDesign For Manufacturability (Dfm)Final Test (Ft)Image SensorsSilicon ProcessWafer Probe Testing
YesterdaySaved
In-Office
Santa Clara, CA, USA
105K-140K Annually
Entry level
105K-140K Annually
Entry level
Semiconductor • Manufacturing
Designs, simulates, verifies, debugs, and characterizes analog and mixed-signal circuits for high-speed interfaces, SerDes, PLLs, CDRs, FIFOs, and clock systems. Collaborates with system and test engineers on image sensor and bridge chip products. Performs high-speed testing with oscilloscopes and BERT, supports layout optimization, verifies analog-digital interfaces, and documents IP and design specifications.
Top Skills: BertCadenceRtlSpectremdlSpice
YesterdaySaved
In-Office
Santa Clara, CA, USA
121K-200K Annually
Entry level
121K-200K Annually
Entry level
Semiconductor • Manufacturing
Designs metasurfaces and diffractive optical structures to manipulate light and improve image sensor performance. Troubleshoots optical issues, develops solutions, performs FDTD simulations and optimization, and analyzes optical and image data using tools such as MATLAB, Python, and Excel. Requires advanced education in optics, physics, electrical engineering, or a related field, along with strong teamwork and communication skills.
Top Skills: Diffractive Optical DevicesExcelFdtd SimulationMatlabMetasurface StructuresPython
YesterdaySaved
In-Office
Santa Clara, CA, USA
105K-140K Annually
Entry level
105K-140K Annually
Entry level
Semiconductor • Manufacturing
Designs, simulates, verifies, debugs, and characterizes embedded analog and mixed-signal circuits for high-speed interfaces, including SerDes, PLLs, CDRs, and clock systems. Collaborates with system and test engineers on package, board, and system-clock development. Performs high-speed testing with oscilloscopes and BERTs, supports analog/digital interface verification, contributes to layout optimization, and documents IP and design specifications.
Top Skills: BertCadenceCdrFifoOscilloscopePllRtlSerdesSpectremdlSpice
YesterdaySaved
In-Office
Santa Clara, CA, USA
157K-160K Annually
Senior level
157K-160K Annually
Senior level
Semiconductor • Manufacturing
Design and develop CMOS image sensor analog and mixed-signal circuits in advanced sub-micron technologies. Perform schematic and layout design, simulation, verification, parasitic extraction, and whole-chip integration using industry-standard EDA tools. Collaborate with digital, verification, process, test, and applications teams to define interfaces, debug fabricated sensors, and optimize performance. Develop scripts for simulation and data analysis, conduct laboratory measurements, and contribute innovative circuit research and development.
Top Skills: Analog FastspiceArduinoAutodesk EagleBluetooth Low EnergyCadence LayoutCadence SpectreCadence VirtuosoCalibre PexCmosDaq SystemsDrcEmpyrean AlpsFinfetFpgaFunction GeneratorsHdlLvsMatlabNanospiceOscilloscopesPcbPercPythonRtlSiemens CalibreXilinx Vivado
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YesterdaySaved
In-Office
Santa Clara, CA, USA
131K-170K Annually
Senior level
131K-170K Annually
Senior level
Semiconductor • Manufacturing
Designs, optimizes, and physically implements column-level ADC circuits for CMOS image sensors. Responsibilities include column layout design, cross-product IP comparison, RCX parasitic extraction, supply and power-routing analysis, floorplan optimization, design-rule development, Calibre SVRF debugging, and SKILL scripting. The role collaborates with circuit designers and cross-functional teams to improve ADC performance, silicon efficiency, image quality, and layout robustness.
Top Skills: Analog CircuitsCalibre SvrfCmosCmos Image SensorsColumn-Level AdcRcx ExtractionSemiconductorSkillTotem
YesterdaySaved
In-Office
Santa Clara, CA, USA
157K-160K Annually
Junior
157K-160K Annually
Junior
Semiconductor • Manufacturing
Develops and integrates CMOS image sensor fabrication processes with foundry partners, managing experimental silicon splits, process flows, schedules, and performance targets. Supports production and design teams by improving yield and sensor performance for mass production. Analyzes wafer and bench data, coordinates characterization testing, communicates technical requirements across internal and external teams, and monitors foundry lot processing to resolve issues and advance future technologies.
Top Skills: Atomic Force Microscopy (Afm)Cleanroom ProcessingCmos Image SensorsElectrical CharacterizationElectron Beam LithographyFluorescence SpectroscopyFourier-Transform Infrared Spectroscopy (Ftir)MicrofabricationOptical CharacterizationPhoto-Luminescence SpectroscopyPhotolithographyReactive Ion EtchingScanning Electron Microscopy (Sem)Semiconductor DevicesSilicon Wafer ProcessingSputteringThermal DepositionTransmission Electron Microscopy (Tem)Uv-Vis Spectroscopy
YesterdaySaved
In-Office
Santa Clara, CA, USA
110K-145K Annually
Senior level
110K-145K Annually
Senior level
Semiconductor • Manufacturing
Develop AI/ML solutions for semiconductor design and verification workflows. Build scalable pipelines that extract and analyze EDA logs, reports, run artifacts, and design metadata. Create models, heuristics, and analytics for STA, DRC/LVS, ECO optimization, debug, and regression acceleration. Integrate solutions into CAD infrastructure, automation systems, schedulers, and design databases while collaborating with EDA vendors.
Top Skills: CdcDftDrc/LvsEdaMachine LearningPerlPythonRtl-To-GdsShellStatic Timing Analysis (Sta)Tcl
YesterdaySaved
In-Office
Santa Clara, CA, USA
111K-140K Annually
Entry level
111K-140K Annually
Entry level
Semiconductor • Manufacturing
Designs and verifies image sensor controls, processing functions, and high-speed USB/MIPI interfaces. Performs full-chip integration, verification, chip bring-up, validation, and debugging. Participates in FPGA development and documents architectures, registers, interfaces, and designs. Requires familiarity with Verilog RTL, simulation, synthesis, static timing analysis, and formal verification, plus knowledge of high-performance, low-power design, FPGA platforms, emulation, and SoC architecture.
Top Skills: Assertion-Based Formal VerificationDspFormalityFpgaMipiSocStatic Timing AnalysisSynthesisUsbVerilog Rtl
YesterdaySaved
In-Office
Santa Clara, CA, USA
121K-151K Annually
Senior level
121K-151K Annually
Senior level
Semiconductor • Manufacturing
Performs failure analysis of image sensor products and customer returns, creates technical reports, and drives corrective actions. Ensures quality across product development, manufacturing, testing, production release, and servicing. Leads quality improvement initiatives, reduces test incidents, improves customer processes, and supports design, test, and supplier quality activities.
Top Skills: Electrical Failure AnalysisImage SensorsSemiconductor Testing
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