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Lead thermal and thermomechanical characterization and qualification of advanced 2.5D/3D semiconductor packages. Develop and calibrate FEA models, define and run warpage/coplanarity/reliability tests, perform lifetime prediction and failure analysis, own DFMEA activities, and produce customer reports on package reliability.

Lead architecture, microarchitecture, RTL design, and technical direction for scalable Network-on-Chip IPs for FPGA platforms. Develop RTL, prototypes, simulation models, and software bring-up; optimize for power, performance, area, and reliability. Guide verification, collaborate with cross-functional teams, mentor engineers, and apply EDA and AI-enabled automation to meet project schedules and quality goals.

Lead and scale a global software IP engineering organization to define strategy, architecture, and delivery of FPGA software IP, libraries, SDKs, drivers, and platform technologies across embedded, AI/ML, networking, DSP, security, and system management. Partner with product, hardware, and customers, drive architecture and CI/CD practices, ensure quality, schedules, metrics, and cross-functional execution for FPGA platform adoption.

Lead SOC and block-level physical implementation from floorplan and power intent through final signoff. Drive STA, power integrity, PPA optimization, and physical verification. Integrate and productize ML/AI optimization into PnR flows. Mentor a team of physical designers, lead cross-functional convergence, define methodology and constraints (SDC/UPF), and represent physical design in architecture and tapeout planning.

Lead backend physical implementation from netlist to GDSII: floorplanning, placement, CTS, routing, ECOs, sign-off, PPA optimization, power and signal integrity analysis, FPGA-specific integration, EDA tool and flow development (Tcl/Python/Perl), manufacturing/package integration, debugging, and mentoring junior engineers.

As a Senior DFT Design Engineer, you will define and implement DFT architectures, perform test logic insertion, collaborate with design teams, and contribute to DFT methodologies.

The Technical Program Manager leads complex technical programs for FPGA device development, coordinating efforts across various engineering disciplines, managing schedules, and ensuring global team alignment.

Oversee and mentor a GUI development team, coordinating global efforts and collaborating with various teams to deliver EDA tools.

The Product Development Engineer drives testability and manufacturability of circuits, performs yield analysis using data science techniques, and interfaces with various engineering teams to optimize silicon yield and quality.

Design and deliver mixed-signal/analog IP (regulators, bandgaps, ADCs, DLLs, SerDes) through schematic, pre/post-layout optimization, verification, collateral generation, and post-silicon debug in advanced CMOS processes while collaborating cross-functionally.