Top Tech Jobs & Startup Jobs

Design, implement, and optimize FPGA placement algorithms to improve timing, congestion, resource utilization, and runtime for large designs. Integrate placement into the compiler flow, collaborate with routing, synthesis, architecture, and timing teams, analyze convergence and QoR, and validate toolchain performance across diverse workloads.

Develop, validate, and maintain ATE test methods and production test programs (wafer sort and final test) using Teradyne/Advantest. Drive product test development through NPI to high-volume manufacturing, analyze silicon across PVT corners, optimize guardbands, reduce test time, debug silicon/test hardware/manufacturing issues, and collaborate with cross-functional teams to support production releases and continuous yield and quality improvements.

Lead physical implementation and STA for advanced FPGA SoCs from floorplanning through final timing closure. Drive block- and SoC-level implementation, develop SDC/UPF constraints, perform MMMC STA with PrimeTime, resolve timing/physical violations, execute signoff/physical verification, build Tcl/Python automation and evaluate ML/AI-assisted flows, and mentor engineers while coordinating with RTL, CAD, library, and packaging teams.

The Treasury Manager will oversee cash flow forecasting, manage global bank accounts, ensure compliance, and lead automation projects in the treasury department.

Responsible for design validation of high-speed protocol IPs, creating verification plans, developing testbenches, and collaborating with teams for implementation and quality improvement.

Lead thermal and thermomechanical characterization and qualification of advanced 2.5D/3D semiconductor packages. Develop and calibrate FEA models, define and run warpage/coplanarity/reliability tests, perform lifetime prediction and failure analysis, own DFMEA activities, and produce customer reports on package reliability.

Lead architecture, microarchitecture, RTL design, and technical direction for scalable Network-on-Chip IPs for FPGA platforms. Develop RTL, prototypes, simulation models, and software bring-up; optimize for power, performance, area, and reliability. Guide verification, collaborate with cross-functional teams, mentor engineers, and apply EDA and AI-enabled automation to meet project schedules and quality goals.

Lead and scale a global software IP engineering organization to define strategy, architecture, and delivery of FPGA software IP, libraries, SDKs, drivers, and platform technologies across embedded, AI/ML, networking, DSP, security, and system management. Partner with product, hardware, and customers, drive architecture and CI/CD practices, ensure quality, schedules, metrics, and cross-functional execution for FPGA platform adoption.

Lead SOC and block-level physical implementation from floorplan and power intent through final signoff. Drive STA, power integrity, PPA optimization, and physical verification. Integrate and productize ML/AI optimization into PnR flows. Mentor a team of physical designers, lead cross-functional convergence, define methodology and constraints (SDC/UPF), and represent physical design in architecture and tapeout planning.

Lead backend physical implementation from netlist to GDSII: floorplanning, placement, CTS, routing, ECOs, sign-off, PPA optimization, power and signal integrity analysis, FPGA-specific integration, EDA tool and flow development (Tcl/Python/Perl), manufacturing/package integration, debugging, and mentoring junior engineers.