Senior Design Automation Engineer - Front End Design Verification

Posted Yesterday
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San Jose, CA, USA
In-Office
188K-271K Annually
Senior level
Artificial Intelligence • Internet of Things • Machine Learning
The Role
Develops and supports automated FPGA and ASIC design verification flows from RTL through GDSII. Responsibilities include building scripting frameworks, integrating and enhancing EDA tools, applying AI/ML to design automation, automating repetitive workflows, improving design infrastructure, and collaborating with design, verification, CAD/EDA teams, and vendors. The role requires extensive experience with front-end RTL, pre-silicon verification, EDA tools, Unix/Linux, Python, Tcl, and Shell.
Summary Generated by Built In
Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

Altera is seeking a Senior Design Automation Engineer to join our Design Methodology, Automation and Infrastructure Team. 

This team is responsible for building and maintaining the core automation infrastructure that supports Altera’s FPGA design flows—from RTL to GDSII. In this role, you will play a critical part in scaling our internal design productivity, delivering highly automated, reliable, and efficient flow systems that accelerate development cycles for next-generation FPGA products.
 

Key Responsibilities of the Senior Design Automation Engineer include but are not limited to:

  • Develop, deploy, and support advanced design automation flows and methodologies for digital semiconductor design.

  • Create scripts, tooling customizations, and automation frameworks leveraging AI-driven tools and systems to streamline complex design processes.

  • Evaluate, integrate, and enhance EDA tools to improve design productivity, efficiency, and quality across the organization.

  • Automate repetitive design tasks, delivering solutions that are robust, scalable, maintainable, and aligned with long-term architecture.

  • Collaborate with design and verification teams to identify workflow bottlenecks and implement impactful process improvements.

  • Drive continuous improvement in design automation infrastructure, methodologies, and best practices.

  • Work closely with internal teams and external EDA vendors to resolve tool issues, influence roadmaps, and adopt new capabilities.

Salary Range 

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.  

$187,900 - $270,700 USD 

We use artificial intelligence to screen, assess, or select applicants for the position.  Applicants must be eligible for any required U.S. export authorizations. 

#LI-MD1

Qualifications:

Minimum Qualifications:

Bachelor’s or Master’s Degree in Computer Science, Electrical Engineering, or related field with 8+ years of relevant industry experience, including:

  • 8+ years of hands-on experience with Front End RTL and or Design Verification EDA tools and FPGA/ASIC design flows (e.g.,VCS, Xcelium, SpyGlass).

  • Experience utilizing AI/ML-driven features within commercial EDA tools and/or building data pipelines and training systems to support learning-based design automation.

  • Proficiency in Unix/Linux environments and scripting/programming languages such as Python, Tcl, and Shell.

  • Experience building flow automation tools and integrating them into complex design pipelines.

  • Ability to collaborate with cross-functional teams and translate user requirements into scalable solutions.

Preferred Qualifications:

  • 10+ years of relevant industry experience with Design Automation tools

  • Experience with Front End Pre-Silicon design verification flows

  • Familiarity with advanced features of EDA tools like Lint/CDC/RDC etc.,

  • Strong communication and collaboration skills, with the ability to partner across design and CAD/EDA teams.

  • Prior experience in large-scale SoC or IP development environments.

Job Type: Regular

Shift:Shift 1 (United States of America)

Primary Location:San Jose, California, United States

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Skills Required

  • Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field
  • 8+ years of relevant industry experience
  • 8+ years of hands-on experience with front-end RTL or design verification EDA tools and FPGA/ASIC design flows
  • Experience using AI/ML-driven features in commercial EDA tools or building data pipelines and training systems for learning-based design automation
  • Proficiency in Unix/Linux environments and Python, Tcl, and Shell scripting/programming
  • Experience building flow automation tools and integrating them into complex design pipelines
  • Ability to collaborate with cross-functional teams and translate user requirements into scalable solutions
  • 10+ years of relevant industry experience with design automation tools
  • Experience with front-end pre-silicon design verification flows
  • Familiarity with advanced EDA tool features including Lint, CDC, and RDC
  • Strong communication and collaboration skills across design and CAD/EDA teams
  • Experience in large-scale SoC or IP development environments

Altera (altera.com) Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).

  • Retirement Support Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
  • Leave & Time Off Breadth Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
  • Parental & Family Support Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.

Altera (altera.com) Insights

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The Company
HQ: San Jose, California
1,612 Employees
Year Founded: 1983

What We Do

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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