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Lead the development of advanced packaging technology for HPC and AI solutions, focusing on architecture, integrity studies, and collaboration with external partners.

Manage physical design and timing closure for high-performance processors, mentor a team, and drive execution and strategy for ASIC solutions.

In this role, you will design, develop, and maintain Windows kernel-mode/device drivers, debug issues, optimize performance, and lead junior engineers.

Lead the development and verification of SoC emulation models, optimize performance, automate flows, and collaborate with design teams.

We are seeking a Timing/STA Engineer with expertise in timing constraints development and STA methodologies for intricate SoC designs. Responsibilities include developing timing constraints, conducting static timing analysis, automating STA processes, and collaborating with cross-functional teams for design optimization.

Seeking a Senior Firmware Engineer to manage firmware for high-speed interconnects, develop APIs, and enhance AI solutions with Celestial AI's technology.

The Senior Principal Digital IC Design Engineer will develop and optimize RTL for high-performance computing, lead design projects, collaborate across teams, and mentor junior engineers on security IP design.

The Staff System QA Engineer will design test plans, validate firmware features, develop automated tests, and support customers in integration.

The Principal System QA Engineer will design and execute test plans, validate firmware features, develop automated tests, and support tier-1 customers with testing integration.

Seeking an experienced ASIC synthesis and design engineer to develop timing constraints and implement ASIC front-end tasks, collaborating across teams for high-speed designs.