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Design and verify mixed-signal circuits like ADCs, PLLs, and amplifiers in CMOS technology while correlating simulations with measurements.

Lead micro-architecture and RTL development for DSP logic within high-performance mixed signal ICs, ensuring timing closure and power optimization.

Lead the design and governance of global compensation programs, ensuring compliance and alignment with strategic goals while managing executive compensation and stakeholder engagement.

The position involves leading DFT architecture and execution for complex ASIC/SoC designs, innovating methodologies and guiding a team of engineers.

Interns will develop embedded firmware in C, test codes in C and Python, and debug issues while gaining experience in the software development cycle and CI methodologies.

Lead SoC design programs from architecture to tape-out, ensuring cross-functional alignment. Responsibilities include RTL design, verification, post-silicon validation, and team mentorship.

The Senior Principal Design Verification Engineer will architect simulation test benches, develop test plans, debug issues, and mentor junior engineers in verifying advanced SoC designs.

The Principal Design Verification Engineer will oversee the verification of chip circuitry, develop verification environments, write test plans, and ensure designs meet specifications through effective collaboration with designers.

The role involves verification of memory subsystems for various SoCs, developing verification components, writing tests, debugging, and providing guidance to junior engineers.

The Principal Engineer will lead verification of SoCs, develop test strategies, and guide a team on pre-silicon validation of memory subsystems, ensuring functional correctness through detailed test plans.