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The Senior Principal Engineer will lead the end-to-end development of a photonic chiplet, integrating electrical and photonic circuits, and ensuring robust system validation through cross-functional collaboration.

Lead and grow an analog layout team delivering high-quality physical layouts for high-speed mixed-signal ICs across advanced nodes. Own execution planning, reviews, methodology, tool deployment, and cross-functional collaboration to ensure timely tapeouts, silicon bring-up support, yield improvement, and continuous process/tool enhancements.

Design, implement, and maintain large-scale, highly available global network architectures including multi-cloud, SD‑WAN, data center, and wireless solutions. Lead complex routing, switching, migrations, disaster recovery, automation, and visibility efforts; build test labs, produce detailed designs and documentation, coordinate carriers, and mentor network team members.

Design high-speed, low-power analog mixed-signal circuits for SerDes and wireline applications in advanced CMOS. Develop blocks (clock generation/distribution, DLLs, ADCs/DACs, CTLE, VGA, TX drivers, regulators), supervise layout, perform post-silicon validation and lab characterization, use EDA tools, collaborate cross-functionally, and prepare documentation and design reviews.

Develop and document SDK software features, deliver releases and sample code, troubleshoot complex SW/API/GUI issues, support customer integration and lab trials, create technical collateral, and collaborate with silicon, validation, and marketing teams to drive product adoption.

The Principal Test Engineer will lead development of ATE test solutions, innovate high-speed testing hardware, craft test plans, and optimize test flows while collaborating with cross-functional teams.

The Principal Engineer will architect simulation test benches, develop and execute test plans, debug failures, and mentor junior engineers in verifying chip designs.

The role involves planning, designing, and verifying digital circuits in SerDes IP, coordinating with cross-functional teams to deliver high-speed communication solutions.

Support customers integrating Marvell Ethernet PHYs through schematic review, board bring-up and debugging, lab/field trials, troubleshooting, technical training, sales support, cross-functional collaboration, and creation of application notes and technical collateral.

Lead implementation of DFT/Test for complex ASIC/SoC and chiplet designs using Tessent and related EDA tools. Define DFT architecture, run insertion flows, generate patterns, support STA constraints, and drive post-silicon bring-up and debug. Mentor a small DFT team and enhance methodologies and tools across multi-die custom compute designs.