Senior Staff Engineer - SerDes Digital Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products

What You Can Expect

ASIC design engineer responsible for planning and coordinating the design, verification, and evaluation of digital circuits in high-speed data communication ICs. The candidate will work closely with digital design, design verification, firmware, and analog design engineers to ensure that projects are completed on time and in high quality.

The responsibilities include but are not limited to:

• Collaborate with Analog/DSP/DV/FW/AE teams to coordinate the delivery of competitive SerDes IP solutions for all the Marvell product lines
• Understand and improve the unique in-house design methodology and flow
• Provide support to the product teams for both pre and post silicon
• Lead the development and execution of RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications
• Work with cross-functional teams to define requirements, create schedules and budgets, manage risks, and communicate with stakeholders
• Develop and maintain relationships with key stakeholders
• Identify and mitigate risks to project success
• Track and report on analog mixed-signal IP development progress
• Continuously improve project execution processes

What We're Looking For

Candidate must have:

• Bachelor degree in Computer Science, Electrical Engineering or related fields and 5-15 years of related professional experience
• Master degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience
• Good personal communication skills and collaborative spirit
• Strong work ethic and motivation to be part of a highly competent design team

Must be proficient in the following skills:

• Fundamental concepts in digital design, design verification, and timing closure (STA) in support of high-speed analog mixed-signal SerDes design
• Concepts in physical and layout design
• Excellent cross-discipline communication and interpersonal skills
• Ability to work independently and as part of a team
• Strong problem-solving and decision-making skills
• Verilog coding

Highly desirable skills:

• Experience with design flow and methodology
• Experience with silicon validation support
• Experience with power analysis and optimization
• Strong Perl and Tcl scripting skill

Expected Base Pay Range (USD)

125,900 - 186,260, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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