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The Firmware Engineer will design, implement, and test embedded firmware for optical components, manage documentation, and collaborate with teams throughout the product lifecycle.

The Director will lead design verification for PCIe and Memory technologies, managing global teams and ensuring high-quality silicon production through UVM-based environments and collaboration with various teams to meet schedules and mitigate risks.

The Principal Application Engineer will lead technical projects, resolve complex issues, and interface with key customers to enhance product deployment in AI and data center platforms, utilizing expertise in hardware systems and DSP technologies.

The Design Verification Engineer will lead complex design verification projects, defining methodologies and ensuring high-quality verification of semiconductor designs across various applications.

The role involves physical design and methodology for advanced processor chips. Responsibilities include collaborating with design teams, implementation, mentoring, and scripting for automation.

The Senior Staff Analog Layout SRAM Engineer will lead SRAM memory layout development, collaborate with circuit designers, ensure verification closures, mentor junior engineers, and develop automation scripts to enhance productivity.

As a Test Development Principal Engineer, you'll develop and optimize testing strategies for semiconductor chips, ensuring they meet customer specifications and performance standards on Advantest 93K platform.

As a Principal Product Engineer, you will lead the entire lifecycle of Ethernet and AI Networking products, managing product introduction, quality improvements, and cross-functional collaboration.

Lead the productization of datacenter connectivity solutions, drive new product introduction from silicon bring-up to mass production, and oversee multiple product ramps while collaborating with global teams.

The role involves developing a functional verification environment, writing and debugging verification test plans, and mentoring junior engineers in SoC verification for high-speed data transfer technology.