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The Identity and Access Management Engineer will design and implement IAM systems, ensuring compliance with security guidelines. This role involves collaborating with cross-functional teams, managing user provisioning, and acting as a trusted adviser on IAM functions. The engineer will leverage knowledge in authentication protocols and IAM technologies to develop secure solutions.

The Analog IC Design Engineer will design sophisticated CMOS transceiver/SERDES products, focusing on circuits like PLL, ADC, and amplifiers. They will also engage in design verification using SPICE and MATLAB, and perform layout activities in nanometric technologies. Interaction with cross-functional teams for design integration and customer support is also expected.

The Senior Staff Finance Manager will lead the FP&A function for the Connectivity Business Unit, involving strategic planning, budgeting, and financial reporting. The role includes managing a finance team, partnering with cross-functional teams, providing financial analysis, and driving process improvements.

The Principal Digital Design Engineer will be responsible for designing critical digital blocks, coding high-quality RTL, and collaborating with various teams to optimize performance. The role involves resolving timings, validating silicon, and leading investigation into design bugs, focusing on innovations for cloud and AI sectors.

The Associate General Counsel leads the Commercial Transactions Group, managing complex commercial agreements primarily for AI and cloud customers. Responsibilities include drafting and negotiating contracts, assessing legal risks, providing legal advice to senior management, and improving legal processes.

The Analog IC Design Engineer will design sophisticated CMOS transceiver products, implementing and verifying complex circuits like PLLs, ADCs, and amplifiers. Responsibilities include design verification using industry-standard tools and resolving technical challenges with expert collaborators.

As a Senior Staff Physical Design Engineer, you will develop the physical design flow for high-performance processor chips, focusing on synthesis, place and route, and timing analysis. You will collaborate with RTL and global timing teams to ensure that designs meet performance goals and assist in methodology development to optimize design processes.