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Create and execute verification plans for complex SoCs. Build constrained-random UVM testbenches in Verilog/SystemVerilog, use Synopsys VCS and Verdi for simulation and debug, write C/C++ and Python scripts, validate RTL and gate-level designs, analyze coverage metrics, and collaborate with design teams to resolve issues.

Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, emulation/PSV efforts to tapeout, bring up ASICs in the lab, mentor and lead cross-functional ASIC development teams, and improve tools and processes to deliver high-quality SoC products.

Design and execute verification plans for complex SoCs using RTL and gate-level simulation. Develop constrained-random UVM testbenches, debug failures with Verdi/VCS, create test vectors, drive coverage models, and collaborate with design teams to validate functionality including AMBA AXI4 and PCIe protocols.

Lead SoC digital design and integration: own chip subsystems, integrate IP blocks, collaborate on floorplan, drive timing closure, run RTL and gate-level simulations, perform CDC and static checks, deliver micro-architectural specs, leverage EDA and automation tools, lead processor IP design, assist verification and post-silicon debug, and mentor junior engineers.

Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, lab bring-up, emulation toward successful tapeout, and lead cross-functional ASIC development teams.

Develop and maintain UVM testbenches and verification collateral for complex SoC architectures. Create test plans and strategies, develop tests to meet coverage goals, debug failures, and collaborate with designers to resolve issues. Support verification environments and regression/bug-tracking workflows.

Develop and maintain UVM-based verification environments and testbenches for complex SoC architectures. Create test plans and coverage-driven tests, debug failures, collaborate with designers, and use SystemVerilog/Verilog, C/C++, and scripting (Python/Perl) on Linux platforms to ensure design quality.

Lead verification architecture, execution, and delivery for next-generation ASICs. Own emulation, post-silicon validation, lab bring-up, and tapeout efforts. Drive DV methodologies, tools, and cross-functional collaboration to ensure high-quality SoC products.

Staff Engineer in Digital IC Design leading digital integrated circuit architecture and RTL design, verification, timing closure, and implementation. Collaborates across teams, drives design reviews, mentors engineers, and ensures deliverables meet performance, power, and area targets while complying with export control requirements.

Design and implement synthesizable RTL (Verilog/SystemVerilog) for digital IP and subsystems. Perform linting, CDC and low-power checks, analyze timing/area/power tradeoffs, support synthesis and timing closure with physical design, debug via simulation/emulation/FPGA/silicon, participate in silicon validation, and mentor junior engineers.