Top Tech Jobs & Startup Jobs

As a Test Development Principal Engineer, you'll develop and optimize testing strategies for semiconductor chips, ensuring they meet customer specifications and performance standards on Advantest 93K platform.

The Senior Principal Program Manager leads complex program execution in semiconductor solutions, managing cross-functional teams and ensuring successful delivery of design initiatives.

Senior individual contributor owning IP release qualification for SoC subsystems: enforce RTL static quality (lint/CDC/RDC), validate synthesis readiness (SDC/UPF), ensure DFT/test readiness, manage IP delivery checklists and packaging, triage integration issues with SoC teams and vendors, and drive cross-functional alignment and automation to meet production-quality schedules.

Leads business strategy, product vision, roadmaps, customer engagement, lifecycle management, revenue growth, design wins, and ecosystem partnerships for Marvell’s silicon photonics, CPO, and AI optical interconnect portfolio. Collaborates with executives, engineering, sales, marketing, operations, hyperscalers, and technology partners to develop products from concept through production ramp. Requires deep semiconductor or optical networking expertise, strategic planning, market analysis, and executive leadership experience.

Leads strategic finance for a multi-billion-dollar semiconductor business unit, partnering with the President on planning, budgeting, forecasting, performance analysis, R&D investment, margins, operational efficiency, M&A, valuation, and partnerships. Manages a global finance team, develops talent, advises senior executives, and drives finance transformation and process improvement.

Drive and improve ML-based demand forecasting, analyze market and sales trends, monitor supply chain KPIs, assess demand plan variances, and lead corrective actions. Manage the S&OP process and collaborate with Sales, Marketing, Finance, Supply Chain, and Business Units on market intelligence, new product introductions, scenario planning, and cross-functional projects.

Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, lab bring-up, emulation toward successful tapeout, and lead cross-functional ASIC development teams.

Design, implement, verify, and document micro-architecture and RTL for complex power-management ASICs. Own end-to-end development from architecture and RTL coding to synthesis, timing closure, formal and gate-level verification, silicon bring-up, documentation, and cross-functional reviews while improving design and verification methodologies.

Lead the SOC design team, manage high-quality SOC designs, integrate IPs, and ensure successful product execution through collaboration and technical leadership.

Design and own core Python-based verification infrastructure: declarative build graph, run-record store, simulator backends, failure bundles, CI/grid integrations, and operational deployment; support AI agents with deterministic guardrails and provide docs and rollout support to DV teams.