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The Corporate Development Manager at Marvell will lead M&A and investment strategies, conduct financial analyses, and collaborate with senior leadership to drive strategic initiatives in the technology sector.

As a Senior Engineer in Physical Design, you will focus on block-level PNR for advanced CMOS chips, performing design checks, timing analysis, and optimization, working with EDA tools and methodologies.

The Principal Analog/Mixed-Signal CAD Engineer will develop automated design flows, support analog design teams, and enhance productivity for advanced silicon programs.

The Senior Staff Digital Design Engineer will lead the design and development of complex ASICs for connectivity solutions, focusing on high-speed datapaths and DSP-driven processing engines in collaboration with architecture and verification teams.

Design micro-architecture for chips, implement low-power RTL, collaborate on verification and physical design, and support silicon bring-up.

Design and verify analog circuits through Verilog/SystemVerilog modeling, support model users, and conduct AMS simulations for functionality verification.

Lead end-to-end DFT implementation and verification for complex SoCs, including MBIST/BISR, boundary scan, IJTAG, ATPG, DFT DRC closure, test coverage improvement, TCL automation, and post-silicon debug working with RTL, Physical Design, and ATE teams.

The Rack Level Integration Engineer will validate and integrate components within AI compute racks, leading design and implementation for performance and reliability.

The role involves physical design of complex chips, methodology development, running synthesis, place and route tools, and performing timing and EMIR analysis checks in a team setting.

Lead the strategy and transformation of FP&A systems at Marvell, focusing on AI integration, modernization of technology stacks, and driving business-critical initiatives.