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Develop, optimize, and maintain embedded firmware for optical engines and photonic integrated circuits, including control and calibration of optical modules and high-speed link optimization.

Lead customer-facing technical engagements for optical connectivity, driving solution adoption, link bring-up, debug, and system validation. Partner with silicon, firmware, hardware, and optical module partners to develop test methodologies, documentation, and field enablement while mentoring engineers and representing the company at industry forums.

The Principal Digital Design Engineer will architect and implement advanced digital designs for AI connectivity, manage complex design blocks, and drive RTL implementations, ensuring production-quality silicon for high-speed protocols.

Lead RTL design and implementation for connectivity silicon blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design teams to achieve timing closure, CDC, lint, and low-power goals. Mentor engineers, debug pre- and post-silicon issues, and drive methodology for timely tapeouts.

Lead architecture and hands-on design of high-speed analog/mixed-signal blocks (SerDes, PLLs, ADC/DACs, references). Define specifications, run PVT/Monte Carlo simulations, drive layout and floorplanning, lead silicon bring-up and characterization, and mentor engineers while collaborating with digital, system, product, and packaging teams.

Lead end-to-end program planning and execution for AMS IP development from specification through tape-out and silicon bring-up. Orchestrate cross-functional teams (circuit design, layout, verification, validation), manage schedules, risks, budgets, and vendor/foundry coordination, and drive process improvements and stakeholder alignment to deliver high-quality silicon on schedule.

Lead advanced packaging R&D for photonics products, defining process flows (wafer/panel/die), integrating EIC-to-PIC, qualifying materials and equipment, partnering with OSATs and vendors, and driving yield, reliability, PDKs, and packaging design rules for NPO/CPO products.

Lead formal verification for complex IP and SoC designs: create formal plans, develop assertions and properties, drive proof convergence, deploy verification flows and tools, mentor engineers, triage bugs, and support verification sign-off to ensure first-pass silicon success.

Lead DFT strategy and execution for multi-die PCIe switch products using 2.5D/3D packaging. Define test architecture, implement scan/ATPG/MBIST/LBIST, drive fault coverage targets, optimize production test and ATE costs, collaborate across design, packaging, validation, and manufacturing to ensure yield, reliability, and production ramp.

The Senior Principal Engineering Program Manager will lead ASIC product development, ensuring timely execution, risk management, and cross-functional alignment across various teams to deliver revenue-critical silicon solutions.