Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
At Astera Labs, we seek a motivated and experienced Tech Lead PCB Layout Engineer to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will design complicated PCB layout across multiple fields including high-speed interfaces, power, high-density interconnect, etc. This position will be onsite.
Basic Qualifications
- Strong academic/technical background in electrical engineering or similar degree; Bachelor’s is required;
- 10+ years of experience designing top-tier complex PCB (40,000+ pins, 30+ layer count) across high-speed differential pairs, RF, high-power, high-density interconnect (HDI), etc.
- Capable of full PCB design process from feasibility study, to DFM and Gerber release.
- Have a proven track record with achieving layout design for signal integrity, power integrity, DFT, and DFM.
- Cross-functional design mentality with the electrical design community to develop systems.
- Self-starting, professional, and hands-on work ethic that can execute intense design work in a dynamic environment.
- Proven track record solving problems independently, preferably as a tech lead.
- Prefer previous work experience with oversee customers and proficient in speaking/written English.
Required Experience
- Proficient in PCB designs with PCIe Gen5/6, Ethernet 112G/224G PAM4, and DDR4/5 applications.
- Proficient in advanced PCB technologies such as micro-vias, blind vias, any layer HDI, back-drilling, and sequential lamination, step gold finger, etc.
- Master EDA tools including Cadence Allegro, Polar SI9000, CAM350 or similar DFM inspection tools, and AutoCAD.
- Proficient in PCB design rules, constraint manager, checklist, etc.
- Possess decent speaking and written English skills.
- Familiar with PCB manufacture and PCB assembly process and capable of handling PCB/PCBA EQ.
Your base salary will be determined based on your experience and the pay of employees in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering
- Master's degree in Electrical Engineering
- 8+ years supporting or developing complex SoC/silicon products for Server and Networking
- 8+ years hands-on high-speed SI/PI design, simulation, and measurement experience
- Experience with SI/PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects
- 2D and 3D EM simulation experience with Cadence, Ansys, ADS or similar toolsets
- EM modeling of BGA and connector structures
- High-speed SERDES channel simulation and equalization experience
- Power integrity (PI) simulations with Ansys/Cadence toolsets
- Hands-on measurement experience with VNA, TDR, real-time and sub-sampling oscilloscopes
- Working knowledge of PCB fabrication limits and trade-offs
- Familiarity with PCI-SIG and IEEE 802.3 electrical standards
- Proven track record defining hardware system constraints and technology roadmaps
- Strong debugging, analysis, and problem-solving skills; experience leading root cause and corrective action teams
- Proven ability to solve problems independently and act as technical lead
- Cross-functional collaboration with electrical design teams
- Authorized to work in the US and able to start immediately
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
-
Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
-
Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
-
Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
