Top Tech Jobs & Startup Jobs

Develop front-end design automation tools and flows supporting verification, lint, synthesis, and package generation. Collaborate with design automation, verification, and development teams to solve engineering problems and support a global digital IP organization. The role requires programming and scripting expertise, SystemVerilog and Verilog proficiency, knowledge of CDC and RDC concepts, and experience automating front-end EDA tools.

Leads sales growth for Rambus Interface IP and Security businesses by managing strategic customer accounts, achieving revenue and design-win targets, forecasting demand, developing account strategies, identifying market opportunities, and building senior-level customer relationships. Partners with marketing and business units to align product launches, customer requirements, investments, and business development initiatives.

Leads sourcing strategy for semiconductor foundry and OSAT suppliers, including supplier negotiations, performance monitoring, cost modeling, procurement planning, project leadership, process improvement, and cross-functional communication. The role manages supply, quality, technology, and cost objectives while supporting strategic sourcing, capital budgeting, cost savings, and supplier performance initiatives.

Leads end-to-end technical programs across multiple engineering teams, managing roadmaps, schedules, milestones, risks, dependencies, resources, and stakeholder communication. Drives alignment among engineering, product, quality, and operations teams while reporting progress to leadership and improving program management processes. The role requires 5–10 years of technical program management experience, an engineering degree, and strong cross-functional leadership skills.

Owns chip and block-level physical design from synthesis and floorplanning through placement, CTS, routing, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout at 28nm and below. The role requires expertise in hierarchical and flat timing flows, low-power design, LEC, power-grid analysis, and DRC/LVS/ERC/PERC verification. Provides technical direction on implementation and signoff flows.

Lead end-to-end physical design implementation for chip-level and major IP blocks, including floorplanning, place-and-route, clock tree synthesis, timing closure, static timing analysis, and physical verification. Automate RTL-to-GDS flows, resolve DRC/LVS/ERC issues, collaborate across design teams to achieve PPA targets, and mentor junior engineers. The role also involves methodology documentation and continuous improvement of physical design processes.

Designs next-generation PCIe Gen6/Gen7 switch ASIC IP from architecture and micro-architecture through RTL implementation, verification support, emulation, and tape-out. Responsibilities include developing synthesizable SystemVerilog, optimizing high-performance pipelines, supporting timing and design closure, debugging silicon and protocol issues, collaborating with verification teams, and mentoring engineers. The role requires strong ASIC/SoC logic design expertise, PCIe knowledge, EDA tool experience, and technical leadership.

Develops SI/PI methodologies, package designs, channel simulations, jitter analyses, and decoupling requirements for DDR memory interface products. Partners with chip layout, package, validation, customers, and lab teams to optimize signal performance, correlate simulations with measurements, and support debugging and product bring-up. Requires deep expertise in high-speed memory or SerDes interfaces, electromagnetic and transmission-line theory, equalization, package and PCB design, and commercial EDA simulation tools.

Designs, architects, simulates, and characterizes high-performance analog and mixed-signal circuits for DDR memory interface chips. Responsibilities include receiver and sampler design, modeling, voltage and timing analysis, analog layout supervision, cross-functional collaboration, post-silicon debugging, and silicon-to-simulation correlation.

Designs, develops, deploys, tests, and supports scalable business applications using Microsoft Power Platform. Builds Power Apps, Power Automate workflows, Copilot agents, Dataverse solutions, Power Pages portals, SPFx components, connectors, APIs, and integrations with Microsoft 365, Power BI, ERP, and Salesforce. Manages governance, application lifecycle processes, deployment pipelines, documentation, user acceptance testing, defect resolution, training, and technical support.