Lead MTS Physical Design

Posted 5 Days Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Expert/Leader
Big Data • Internet of Things • Software
The Role
Lead end-to-end physical design implementation for chip-level and major IP blocks, including floorplanning, place-and-route, clock tree synthesis, timing closure, static timing analysis, and physical verification. Automate RTL-to-GDS flows, resolve DRC/LVS/ERC issues, collaborate across design teams to achieve PPA targets, and mentor junior engineers. The role also involves methodology documentation and continuous improvement of physical design processes.
Summary Generated by Built In
Overview

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.

Responsibilities
  • Own end-to-end physical implementation for major IP blocks and/or full-chip designs.
  • Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis)
  • Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus).
  • Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes.
  • Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability.
  • Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements.
  • Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones.
  • Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability.
  • Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement.
  • Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results
Qualifications
  • Must have minimum Bachelors degree in EE/ECE (degree’s related to electronics) from a reputed institute.
  • Must have at least 10 years of experience, out of which at least 8 years should be related to physical design at chip level / block level.
  • Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired
  • Experience in Tcl/Tk, PERL is a Plus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard.Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .

Skills Required

  • Bachelor’s degree in Electrical Engineering, Electronics and Communication Engineering, or a related electronics field from a reputed institute
  • At least 10 years of professional experience
  • At least 8 years of chip-level or block-level physical design experience
  • Detailed knowledge of EDA tools and physical design flows
  • Experience with Cadence-related foundation flows and RTL2GDS flow
  • Experience with Tcl/Tk
  • Experience with Perl
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The Company
HQ: San Jose, CA
989 Employees

What We Do

Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our architecture licenses, IP cores, chips, software, and services span memory and interfaces, security, and emerging technologies to positively impact the modern world. We collaborate with the industry, partnering with leading chip and system designers, foundries, and service providers. Integrated into tens of billions of devices and systems, our products and technologies power and secure diverse applications, including Big Data, Internet of Things (IoT) security and much more!

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