PE Physical Design

Posted 5 Days Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Expert/Leader
Big Data • Internet of Things • Software
The Role
Owns chip and block-level physical design from synthesis and floorplanning through placement, CTS, routing, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout at 28nm and below. The role requires expertise in hierarchical and flat timing flows, low-power design, LEC, power-grid analysis, and DRC/LVS/ERC/PERC verification. Provides technical direction on implementation and signoff flows.
Summary Generated by Built In
Overview

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Physical engineer to join our Physical Design team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.


Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities
  • Complete ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification,
  • Take complete ownership for implementation of both Top/Block level designs.
    • Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out  on 28nm nodes or below.
    • Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM, Timing Closure, constraint (sdc) development)
    • Well versed with the block and chip level timing closure (STA) and timing closure methodologies. Also need to have experience with constraints development. Experience in Hierarchical and Flat timing flow bring-up and timing analysis on interface paths. Block level/Fullchip/SOC level/Mixed signal timing path analysis and fixing.
    • Must have knowledge of low power design. (cpf, upf CLP).
    • Should be able to provide clear directions to the team on various implementation and signoff flows
    • Should be well versed in LEC flow and debugging issues independently.
    • Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
    • Role involves analyzing DRC, LVS,ERC and PERC rule files for industry standard layout verification.
Qualifications
    • ust have minimum Bachelors degree in EE/ECE (degree’s related to electronics) from a reputed institute.
    • Must have at least  10 years of experience, out of which at least 8 years should be related to physical design at chip level / block level.
    • Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired
    • Experience in Tcl/Tk, PERL is a Plus

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.

 Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.


Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others. Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation. At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard.

Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.


Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures. If you require assistance or an accommodation due to a disability, please feel free to inform us in your application.


Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.


For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

Skills Required

  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related electronics discipline
  • At least 10 years of professional experience
  • At least 8 years of chip-level or block-level physical design experience
  • Experience with physical design activities from floorplan through GDS, including synthesis, placement, routing, CTS, extraction, timing closure, physical verification, DFM, and tapeout
  • Experience with 28nm or smaller process nodes
  • Detailed knowledge of EDA tools and physical design flows
  • Experience with block-level and full-chip timing closure, STA, timing constraints, and SDC development
  • Knowledge of low-power design using CPF, UPF, and CLP
  • Experience with LEC flows and independent debugging
  • Experience with power estimation, power-grid design and analysis, static IR drop, and dynamic IR drop
  • Experience analyzing DRC, LVS, ERC, and PERC rule files
  • Cadence foundation flows and RTL2GDS flow experience
  • Experience with Tcl/Tk
  • Experience with Perl
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The Company
HQ: San Jose, CA
989 Employees

What We Do

Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our architecture licenses, IP cores, chips, software, and services span memory and interfaces, security, and emerging technologies to positively impact the modern world. We collaborate with the industry, partnering with leading chip and system designers, foundries, and service providers. Integrated into tens of billions of devices and systems, our products and technologies power and secure diverse applications, including Big Data, Internet of Things (IoT) security and much more!

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