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The role involves building and validating virtual/hybrid prototypes, optimizing system models, and helping customers with software validation. You will interact with engineering teams and provide feedback to improve technological tools.

Seeking a Sr Principal Design Engineer with 12-14 years in VLSI, expertise in Verilog, HVL, UVM/OVM methodologies, and scripting skills.

The Sr Principal Customer Engagement Engineer engages with customers to address their design and verification issues, collaborates with RnD for solutions, and leads technical campaigns while ensuring effective communication in English and Korean.

As a Sr. Principal Software Engineer, you will work on Virtuoso Electrically Aware Design (EAD), debug complex problems, produce innovative solutions, and mentor junior members.

Provide technical support for Cadence's software tools in semiconductor design. Engage with customers and collaborate with other departments. Basic programming and English skills required.

Design and develop high-speed memory PHYs, overseeing sub-systems and mentoring teams while ensuring quality and schedule adherence.

Design and implement verification environments for pre-silicon, create test plans, debug issues, and develop tools for testing Digital Design and SoCs.

Design and optimize meshing algorithms, implement mesh generation techniques, and mentor junior developers to enhance meshing technology integration.

The Lead Software Engineer at Cadence will support R&D for application engineers, analyze/debug problems, and develop features for electronic design software.

The Lead Software Engineer will design, develop, troubleshoot, and debug complex software while collaborating within a team oriented environment. Strong communication skills and ability to learn new technologies quickly are essential.