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The Product Engineer II will develop Conformal expertise within regional teams, lead deployment of Conformal products, conduct training and seminars, capture customer feedback for tool enhancements, and collaborate with R&D to address customer issues. A strong background in ASIC implementation and programming skills in Tcl and Python is required.

The Sr. Principal Software Engineer will provide R&D support for customer-related issues, analyzing and fixing problems, as well as developing new features. The role requires significant problem-solving and innovative research in the EDA domain, with opportunities for mentoring in software engineering skills.

The Sr Principal Digital Verification Engineer will work on the architecture and management of verification environments for complex IP, develop self-checking regressions and functional coverage, and create automated regression environments while collaborating closely with design engineers.

The Senior Principal Design Engineer at Cadence is responsible for developing software for embedded processors and emulation platforms, focusing on efficient algorithms and data structures. The role demands strong programming skills in C/C++ and experience in firmware programming. Additionally, the engineer will collaborate with teams and customers while potentially engaging in international travel. A solid foundation in computer architecture and understanding of Neural Networks is beneficial.

As a Senior Account Technical Executive I, you will manage strategic accounts at Cadence, maximizing the value of their technology solutions, grow product adoption, and drive technical sales engagements. You will develop strategies, build relationships with stakeholders, and coordinate with internal teams to meet customer challenges and sales targets.

The Principal Design Engineer will lead design verification projects, ensuring complex designs are verified from concept to closure. Key responsibilities include environment planning, test plan generation, and developing functional verification environments using System Verilog and UVM.

As a Principal Design Engineer, you will be responsible for the verification of Serial and Interface Design IPs, utilizing UVM testbench development for efficient verification and participating in formal verification and emulation qualification. The role requires strong analytical, problem-solving skills, and effective communication capabilities.