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Lead design verification for interconnect IP and Tensilica processor subsystems. Create and execute verification plans, build UVM-based environments, manage coverage closure, collaborate with DV/Arch/Design/FW teams, and use simulation/debug tools and automated flows to validate complex configurable designs.

Lead design verification for interconnect IP and Tensilica processor subsystems. Create and execute verification plans, collect and close coverage, develop UVM-based DV environments, work with cross-functional teams, and use simulation, gate-level and automated flows for complex configurable designs.

The Lead Product Engineer will certify the Cadence Innovus Platform, collaborate with RD and foundry partners, and resolve complex technical issues for customers.

The Sr Principal Design Engineer will lead complex Silicon programs, define next generation Chiplets, integrate IP solutions, and guide technical teams. Responsibilities include quality assurance, planning activities, cross-functional meetings, and representing Cadence at conferences.

The Principal Design Engineer will work on PCIe design, focusing on high-speed interfaces and collaboration with DV teams to optimize designs and address issues.

The role involves certifying the Cadence Innovus Platform, collaborating with RD and foundry partners, and supporting customers with technical challenges.

The Principal Program Manager coordinates R&D Development Projects and manages customer engagement, ensuring project success through collaboration and effective execution.

Serve as primary technical interface for customers on schematic capture and PCB front-end flows. Diagnose complex schematic and netlisting issues, provide training and demos, translate customer needs into EDA workflows and automation, collaborate with R&D and product teams, create knowledge articles, and lead small technical teams as needed.

Customer-facing principal engineer supporting RFIC, RF module and multichip module designers. Advise on heterogeneous integration, EM and thermal analysis, parasitic extraction and Cadence custom tool flows; deliver trainings, demos, evaluations, and collaborate with sales, engineering and marketing to drive solutions.

Customer-facing Application Engineer deploying Cadence verification platforms and methodologies. Develop subsystem/SoC verification requirements, create UVM/C tests, support pre/post-silicon (simulation, emulation, FPGA, bring-up), run benchmarks, and deliver technical presentations and demos to ensure customer success.