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The Solutions Engineer II develops PERC decks for Cadence's Physical Verification tool, collaborating with R&D and customers to tackle performance issues.

Collaborate with R&D and foundry partners to develop PERC decks for Cadence Physical Verification tools, addressing product issues and improving performance.

Develop efficient PERC decks for Cadence Physical Verification tools, collaborate with R&D and customers to address product issues and enhance performance.

This role involves collaborating with R&D on EA feature development and providing customer use case details. Additionally, it focuses on AVIP support in APAC as needed.

As a Lead Application Engineer, you will enhance customer productivity, debug issues, collaborate on product improvements, and provide innovative solutions.

Develop performance models, perform architectural tradeoff analysis, and enable data-driven design decisions for DDR memory controller architectures.

Develop and maintain AI applications for verification tools, apply AI to engineering problems, and educate peers on AI best practices.

The Product Engineer II will develop and manage PEGASUS/PVS tools while collaborating with customers and R&D to enhance product quality and requirements.

The Principal Design Engineer leads the Functional Safety Design Verification Team, developing and verifying safety mechanisms in hardware and software for Xtensa processors, while ensuring compliance with safety standards.

The role involves IP integration, verification, and release, focusing on RTL integration and debugging, with significant required experience in design processes.