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Develop compiler technology for Cadence’s Palladium hardware emulation platform. Design scalable solutions for large compilation workloads, including model and structural checking. Build, debug, test, and maintain production-quality C/C++ software in Linux/Unix environments, applying multithreading and distributed computing. Collaborate with global engineering teams on design, validation, and issue resolution.

Lead functional verification for Cadence memory controller IP. Develop and enhance UVM-based verification environments, create test plans, validate customer configurations through regression testing, analyze functional and code coverage, support customers using the environment, and ensure designs meet technical and quality requirements.

Develop and verify simulation-efficient analog behavioral models for analog and RF blocks using SystemVerilog. Integrate models with RTL, validate them against analog schematics and design specifications, and create testbenches, scenarios, and assertions. The role also involves low-power architecture, Cadence Virtuoso and ADE workflows, documenting verification results, and collaborating with an engineering team. New graduates are encouraged to apply; DSP, FPGA prototyping, and testbench development experience are beneficial.

Provides technical presales, configuration, demonstrations, and customer support for Cadence high-speed SerDes interface IP. Presents IP capabilities, serves as a protocol and product expert, collaborates with sales, marketing, and R&D teams, supports customer opportunities, leads productivity initiatives, and creates technical content. Requires expertise in high-speed protocols including PCIe, CXL, Ethernet, or USB, along with strong presentation and communication skills.

Leads technical presales and customer solutions for Cadence SerDes design IP, including PCIe, CXL, Ethernet, and other high-speed interface PHYs and controllers. Presents product capabilities, configures IP, demonstrates performance, supports customers and field teams, collaborates with sales, marketing, and R&D, and develops technical content. The role also leads productivity initiatives and may require occasional customer-site travel.

Develop and enhance Cadence’s Xcelium RTL/logic simulator and timing-constraint verification technology. Design and optimize graph algorithms for massive SDC constraint graphs, perform C/C++ performance tuning, reduce compilation time and memory usage, write specifications and unit tests, and collaborate with globally distributed engineering teams.

Architect and enhance Cadence’s Xcelium RTL/logic simulator and timing constraints verification technology. Design scalable graph algorithms for multi-billion-node graphs, optimize C/C++ performance and memory usage, develop specifications and unit tests, lead junior engineers, and collaborate with global teams on semiconductor verification software.

Own post-sales customer success for strategic engineering software accounts. Drive adoption, value realization, customer health, retention, expansion, executive business reviews, and advocacy programs. Build relationships with technical and executive stakeholders, coordinate cross-functional teams, represent customer feedback internally, and support account planning. The role requires technical credibility in CAE and engineering software, strategic account management, customer engagement, and commercial acumen.

Lead complex, high-stakes EDA software development programs across engineering, QA, design, operations, and business teams. Own customer-facing project delivery, establish scope and milestones, manage risks and dependencies, coordinate resources, report to stakeholders, remove blockers, and promote Agile, Scrum, Waterfall, and AI-assisted project management practices.

Drive revenue growth for Cadence physical systems simulation solutions across an assigned European territory. Manage enterprise sales cycles from prospecting through closing, develop strategic relationships with engineering and R&D leaders, and sell CAE, FEA, CFD, and multiphysics software. Identify expansion opportunities, collaborate with technical sales and product teams, maintain pipeline forecasts, analyze market trends, and represent the company at industry events. The role requires up to 30% travel across Europe.