Qualifications • New graduates strongly encouraged to apply! • Experience in developing and verifying real-numbered behavioral models in SystemVerilog • Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS • Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc • Working experience in low power Architecture • Working experience in Cadence Virtuoso Schematic Composer and ADE • Experience with Analog Assertion Based Verification • Experience in TB development will be a strong plus • Experience in writing scripts in languages such as Perl or Python • Excellent teammate with excellent communication skills • Experience with FPGA prototyping is a plus Responsibilities • You will become part of a hands-on development team that fosters engineering excellence, creativity, and innovation. • As an AMS Verification Engineer, you will be responsible for Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog. • Verifying that the behavior models are accurate representations of analog schematics • Integrating the models with RTL • Verifying analog functionalities against design specifications using analog behavioral models: for example, coding test benches, test scenarios, and assertions. • DSP experience a huge plus. Documenting modeling and verification results for formal review We’re doing work that matters. Help us solve what others can’t
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Experience developing and verifying real-numbered behavioral models in SystemVerilog
- Understanding of SystemVerilog, RNM, UDN, UDT, UDR, wreal, and Verilog-AMS
- Basic understanding of AMS blocks, including filters, ADCs, DACs, VCOs, A/DPLLs, SerDes, LNAs, and mixers
- Working experience with low-power architecture
- Working experience with Cadence Virtuoso Schematic Composer and ADE
- Experience with analog assertion-based verification
- Excellent teamwork and communication skills
- Testbench development experience
- Perl or Python scripting experience
- FPGA prototyping experience
- DSP experience
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
