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Leads digital architecture, RTL design, low-power design, synthesis, timing analysis, and tool-flow execution for power-management ICs. Drives designs from architecture through RTL, verification, implementation, system-level bring-up, and post-silicon validation. Collaborates with analog, digital, verification, architecture, and project-management teams globally while improving design processes, reuse, and quality. Applies expertise in ASIC and mixed-signal development, digital control peripherals, power-converter architectures, and power-performance-area trade-offs.

Develop and execute ASIC verification plans, build SystemVerilog OVM/UVM testbenches, implement reusable VIP, and achieve code and functional coverage closure. Apply constraint-random verification, assertions, object-oriented programming, and ASIC verification methodologies. Collaborate with internal teams, external customers, and VIP providers while addressing complex semiconductor design challenges. Low-power UPF and formal verification experience are advantageous.

Leads early product development for SiC power MOSFET technologies, including process integration, engineering lots, DOE, yield and defect analysis, TCAD simulation, cost reduction, and production issue resolution. The role optimizes device performance, reliability, and manufacturing yield through process and design improvements, correlates electrical and process data, supports layout and test structure reviews, enables technology ramp-up, collaborates cross-functionally, and mentors junior engineers.

Leads development of complex power management analog and mixed-signal ICs, from architecture and IP definition through verification, tapeout, silicon evaluation, and manufacturing release. Provides technical leadership, resolves complex analog and silicon issues, guides layout and verification teams, manages schedules and resources, collaborates across systems, applications, validation, product engineering, and test, and mentors junior engineers.

Lead digital design architecture and end-to-end IP or SoC development for power management products. Own RTL implementation, low-power design, synthesis, timing analysis, physical-design interfaces, and front-end tool-flow deployment using RTL2GDS methodologies. Collaborate with analog, digital verification, architecture, project management, and global engineering teams. The role requires leadership in complex ASIC and mixed-signal chip development, platform-based design, microprocessor interconnect integration, and successful IC product releases.

Supports customer experience initiatives through survey and feedback platform management, customer journey projects, data analysis, governance materials, communications, sprint planning, process documentation, and user acceptance testing. Collaborates with cross-functional teams, attends meetings, contributes to brainstorming, and shadows CX leaders and analysts. The internship requires strong communication and organizational skills, Microsoft Office familiarity, interest in customer experience and human-centered design, and enrollment in a relevant degree program.

Coordinates critical and expedited shipments across factories, supply chain, customer service, distribution centers, and freight partners. Analyzes shipment urgency, determines optimal shipping methods, approves expedited requests, monitors deliveries end to end, develops customer recovery plans, and coordinates urgent semiconductor device shipments across regional command centers.

Design and deliver complex analog and mixed-signal power-management IPs, including regulators, converters, gate drivers, and control loops. Lead analog blocks from definition through tape-out, perform design and simulation, guide physical designers, collaborate with validation and test teams, debug silicon issues, and ensure technical execution aligns with full-chip schedules.

Leads digital architecture, RTL design, low-power implementation, synthesis, timing analysis, and verification support for power management ASICs and mixed-signal ICs. Drives designs from architecture through RTL, pre-silicon bring-up, implementation, and post-silicon validation. Collaborates with analog, digital verification, architects, and project teams across global locations while improving design tools, flows, reuse, and quality processes.

Provides HR operational support across recruitment, candidate coordination, interview scheduling, job postings, onboarding, employee data maintenance, reporting, and process improvement. Partners with hiring managers, Talent Acquisition, HR Business Partners, IT, Facilities, Payroll, and shared services teams to ensure efficient hiring and new-hire integration. Requires strong organization, communication, confidentiality, Microsoft Office proficiency, business-level English, and fluent Korean.