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Leads digital architecture, RTL design, low-power implementation, synthesis, timing analysis, and verification support for power management ASICs and mixed-signal ICs. Drives designs from architecture through RTL, pre-silicon bring-up, implementation, and post-silicon validation. Collaborates with analog, digital verification, architects, and project teams across global locations while improving design tools, flows, reuse, and quality processes.

Provides HR operational support across recruitment, candidate coordination, interview scheduling, job postings, onboarding, employee data maintenance, reporting, and process improvement. Partners with hiring managers, Talent Acquisition, HR Business Partners, IT, Facilities, Payroll, and shared services teams to ensure efficient hiring and new-hire integration. Requires strong organization, communication, confidentiality, Microsoft Office proficiency, business-level English, and fluent Korean.

Leads and develops a standard cell library engineering team in Brno. Responsibilities include setting priorities, coordinating projects, ensuring high-quality and timely delivery, guiding circuit design, layout, characterization, modeling, verification, and automation, and improving engineering workflows. The manager also supports recruiting, mentoring, career development, stakeholder communication, and technical project execution across global teams.

Leads digital architecture, RTL implementation, low-power design, synthesis, timing analysis, and verification flows for power management ICs. Collaborates globally with analog, digital, verification, and project teams; supports pre-silicon platforms, post-silicon validation, IP quality control, and system-level feature bring-up. The role requires expertise in ASIC and mixed-signal development, power converter architectures, digital control peripherals, and power-performance-area trade-offs.

Design and deliver analog power-management IP blocks from definition through tape-out. Responsibilities include CMOS analog design, block-level simulation, technical reviews, layout guidance, silicon validation, debugging, and collaboration with product, test, validation, and physical design teams. The role covers regulators, converters, control loops, mixed-signal designs, gate drivers, and other power-management circuits while coordinating execution with full-chip schedules.

Leads analog IP development for power management ICs from definition through tape-out, silicon evaluation, validation, and production transfer. Guides physical design and verification teams, collaborates globally, resolves complex silicon issues, and owns technical outcomes across analog and mixed-signal designs. The role also requires planning schedules and resources, tracking execution, and mentoring or attracting engineering talent.

Lead development of complex analog IPs and power management ICs from architecture and circuit design through verification, layout, silicon evaluation, and manufacturing release. Provide technical leadership, resolve complex analog issues, guide physical and verification teams, manage schedules and resources, and collaborate with systems, applications, marketing, validation, product engineering, and test teams.

Leads development and manufacturing release of complex analog power-management ICs, including DC-DC PMICs, multiphase controllers, gate drivers, converters, and mixed-signal designs. Owns architecture, circuit design, verification, layout oversight, silicon evaluation, debugging, and production transfer. Collaborates with systems, validation, product, test, marketing, and physical design teams while managing schedules, resources, technical outcomes, and engineering talent.

Develops, debugs, qualifies, and supports wafer-level electrical test programs and probe operations for high-power, high-voltage semiconductor devices. Investigates testing and yield issues, analyzes data, qualifies new tools, performs bench tests, and supports manufacturing teams. Collaborates globally with product engineering, device characterization, process integration, and manufacturing groups to improve test accuracy, throughput, product characterization, and production capacity.

Leads analog IP development for power management ICs from architecture and circuit design through verification, tapeout, silicon evaluation, and manufacturing release. Provides technical leadership, resolves complex analog issues, guides physical design and layout, coordinates cross-functional teams, manages schedules and resources, and supports product definition, validation, testing, and production transfer.