Top Tech Jobs & Startup Jobs

Provide hands-on CAD tool flow development and day-to-day support for advanced-process node layout and design issues. Develop and maintain Calibre DRC/LVS decks, CAD PDK environments, EDA simulation flows (Spectre, Hspice), and block-level place-and-route flows. Support QA, testing, releases, user support, documentation, and productivity utilities.

Lead end-to-end power strategy for complex SoCs: define budgets, perform dynamic and leakage analysis across RTL-to-silicon, build automation and power-analysis flows, drive active power reduction (clock/power gating, DVFS), and collaborate with physical, architecture, board, and systems teams for PDN, IR/EM, thermal, and validation.

Provide phone, email, and web technical support for Brocade/Broadcom OEMs and customers. Troubleshoot SAN and networking issues, analyze protocol traces, document service requests, replicate problems in lab, define resolution plans, and collaborate with global teams to close incidents and improve support processes.

Lead EMEA application engineering for vKS, translate global vKS vision into regional programs, engage executives, guide solution architecture across container, infrastructure and DevOps domains, support presales and delivery, capture product feedback, and build and mentor a regional team to scale enterprise Kubernetes adoption.

Design full-custom I/O and analog mixed-signal layouts in planar and FinFET processes; drive floorplanning and power/IO planning; perform comprehensive layout verification (DRC/LVS/ANT/ERC/DFM, LPE, PERC, EM/IR); own end-to-end deliverables, mentor juniors, and collaborate across sites to meet schedules and quality targets.

Design and deliver high-quality memory layouts for advanced FinFET processes. Manage floor-planning, schedule, and chip integration; perform physical verification (LVS/DRC/ERC/Antenna/EM); lead and train layout teams; document methodologies and adapt to new process rules and automation.

Design full-custom I/O and analog mixed-signal layouts in planar and FinFET technologies, own end-to-end deliverables, drive floorplanning and power/IO planning, perform comprehensive layout verification (DRC/LVS/ANT/ERC/DFM, extraction, EM/IR), debug layouts, and lead/train junior engineers while coordinating across sites.

Lead and execute high-impact AI initiatives, serving as a technical authority on agentic systems and fullstack development, while mentoring and optimizing infrastructure strategy.

The Principal IC Design Engineer will design DRAM interface logic, lead simulation and verification efforts, collaborate with teams, and ensure quality designs in SOC architecture.

Design and develop motion control sensors/products, integrate cross-discipline information, and provide engineering support. Requires strong troubleshooting and project management skills, with a focus on new technology advancements.