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Lead IT and operational audit engagements, perform SOX/ITGC testing, assess control deficiencies, support remediation and attestations, coordinate with external auditors, and advise IT/Finance on control improvements and emerging risks such as AI governance.

Design and deliver OS-level and container platform features integrated with ESXi and vSphere. Architect scalable container runtimes, Kubernetes platform capabilities, and distributed control planes. Develop and optimize user-space OS services, contribute security fixes upstream, collaborate with product, UX, and cross-functional teams to produce reliable, high-performance infrastructure for cloud-native workloads.

Lead SoC DFT programs from specification through implementation, verification, and production release. Responsibilities include DFT architecture, scan/ATPG insertion and compression, pattern generation, ATE validation and silicon debug, yield improvement, STA cooperation, customer interfacing, and automation of DFT and vector-generation flows.

Design and verify CMOS I/Os and analog/mixed-signal blocks (bandgap references, op-amps, comparators, POR). Run SPICE/Spectre simulations for AC/DC, SI, jitter, and power. Perform transistor reliability/EM/IR analysis, build Verilog/Liberty/IBIS models, collaborate with layout for physical design and verification, produce technical documentation, and support chip integration and silicon bring-up.

Lead product management and marketing for ANS security and application delivery products (vDefend, Avi). Evangelize solutions to sales, partners, and customers; define use cases and GTM strategy; build messaging and collateral; collaborate with product, architects, PR; speak at industry events; manage high-productivity teams and apply AI to product and marketing strategies.

Lead full-chip static timing analysis and sign-off for ASICs, develop and maintain SDC constraints for multiple modes, manage MMMC timing scenarios, implement timing ECOs, and automate flows using Tcl/Python/Perl. Collaborate with RTL, physical design, and DFT teams to resolve timing, signal integrity, and IR-drop issues while incorporating foundry derates and documenting best practices.

Lead top-level chip floorplanning and partitioning, manage clock tree and I/O/bump planning, resolve physical-design integration and DRC/LVS/EMIR issues, collaborate with package/methodology teams, and develop/improve floorplanning methodologies and vendor/IP evaluations.

Provide pre- and post-sales technical support for high-speed interconnect PHY products, debug hardware/firmware/board issues, review schematics/layouts, analyze customer architectures, train customers and FAEs, and support product definition and roadmap to secure customer design wins.

Perform full-chip physical IC design from RTL to tape-out including synthesis, place-and-route, timing closure, clock tree synthesis, floorplanning, EM/IR analysis, physical verification, methodology development, and collaboration with RTL engineers. On-site role in San Jose.

Design and verify chip-level DFT architecture and implement DFT schemes (scan, boundary scan, MBIST, Logic BIST, SSN). Verify DFT logic and test patterns via simulation, perform test-modes STA, support ATE bring-up and debug, and work across RTL, synthesis, timing verification, physical design, vector generation, and post-prototype test support for advanced node ASICs.