Broadcom

IC Design Engineer (DFT)

Posted One Month Ago

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Hiring Remotely in Zhangjiang, Shanghai Municipality, Shanghai, CHN

Remote

Senior level

Software • Semiconductor • Manufacturing

The Role

Design and verify chip-level DFT architecture and implement DFT schemes (scan, boundary scan, MBIST, Logic BIST, SSN). Verify DFT logic and test patterns via simulation, perform test-modes STA, support ATE bring-up and debug, and work across RTL, synthesis, timing verification, physical design, vector generation, and post-prototype test support for advanced node ASICs.

Summary Generated by Built In

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Job Description:

Broadcom offers an excellent opportunity to contribute to a team environment and to grow personal career path. You will be working with internal and external customers to develop state of the art IC solutions utilizing Broadcom's leading edge CMOS cell-based ASIC technologies. You will have responsibility for ASIC designs through all of the key development and implementation phases including RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support. Candidates will have opportunity to work on the latest 5nm/3nm designs

Responsibilities:

Participate in chip level DFT architecture definition.
Implement basic DFT schemes, including scan, boundary scan, MBIST, Logic BIST and SSN
Verify all DFT logics and test patterns with simulation
Test modes static timing analysis
Participate in ATE bring-up and debug the DFT patterns on ATE.

Requirements/Qualifications:

Either Bachelor or Master degree, 5+ years related experience required.
Good understanding of the General DFT methodology such as BIST, SCAN, JTAG and ATPG
Be familiar with basic Mentor/ Synopsys DFT flow and tools
Experience in developing constraints for synthesis/STA
Multi-mode, multi-corner STA experience, Understanding Sign-Off Checks

Education/Certifications
Preferred Degree: MS Preferred Major: Microelectronics or related discipline

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

Bachelor or Master degree in Microelectronics or related discipline
MS degree preferred
5+ years related experience
Good understanding of DFT methodology (BIST, SCAN, JTAG, ATPG)
Familiarity with Mentor and Synopsys DFT flow and tools
Experience developing constraints for synthesis and static timing analysis (STA)
Multi-mode, multi-corner STA experience and understanding of sign-off checks
Experience with ASIC design flow: RTL analysis, synthesis, timing verification, simulation, test insertion, physical design, vector generation, post-prototype test support
Experience with ATE bring-up and debugging DFT patterns

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

Equity Value & Accessibility — Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
Retirement Support — A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
Pay Growth & Progression — Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.